Initializing Multisim Live ...

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U1U2110kโ„ฆR110kโ„ฆR2242.57nFC110kโ„ฆR311.9nFC253710kโ„ฆR4Vout230.92pFC3028.75nFC41V60Hz0ยฐV2600 V
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ID:

ID:

x10
x0.1
Sheet:1
V
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SPICE
SPICE Netlist

This is a text-based representation of the circuit.
The * symbol indicates a comment.
The + symbol indicates a continuation from the previous line.
Probes do not appear in netlists.

** Passa Baixa 2ยช ordem - VCVS **
*
* Multisim Live SPICE netlist
*
*

* --- Circuit Topology ---

* Component: C1
cC1 4 0 2.57e-9

* Component: C2
cC2 2 1 1.19e-8

* Component: C3
cC3 5 0 2.3092e-10

* Component: C4
cC4 7 3 2.875e-8

* Component: R1
rR1 3 2 10000 VIRTUAL_RESISTANCE_R1

* Component: R2
rR2 2 4 10000 VIRTUAL_RESISTANCE_R2

* Component: R3
rR3 7 5 10000 VIRTUAL_RESISTANCE_R3

* Component: R4
rR4 6 7 10000 VIRTUAL_RESISTANCE_R4

* Component: U1
xU1 4 1 1 3T_VIRTUAL_U1 PARAMS: VOS=0 IBS=0 IOS=0 AVOL=200000 BW=100000000 RI=10000000 RO=10 VOMP=12 VOMN=-12

* Component: U2
xU2 5 3 3 3T_VIRTUAL_U2 PARAMS: VOS=0 IBS=0 IOS=0 AVOL=200000 BW=100000000 RI=10000000 RO=10 VOMP=12 VOMN=-12

* Component: V2
vV2 6 0 dc 0 ac 1 0
+ distof1 0 0
+ distof2 0 0
+ sin ( 0 1 60 0 0 0 )


* --- Circuit Models ---

* R1 model
.model VIRTUAL_RESISTANCE_R1 r( )

* R2 model
.model VIRTUAL_RESISTANCE_R2 r( )

* R3 model
.model VIRTUAL_RESISTANCE_R3 r( )

* R4 model
.model VIRTUAL_RESISTANCE_R4 r( )


* --- Subcircuits ---

* U1 subcircuit
.SUBCKT 3T_VIRTUAL_U1 in_pos in_neg out PARAMS: AVOL=500k BW=10Meg RI=10Meg RO=0 VOS=0 IBS=0 IOS=0 VOMP=15 VOMN=-15

* Input Stage: Rin, Ibias, Voffset
VOS in_pos 4 {VOS}
Ibias1 4 0 {IBS}
Ibias2 in_neg 0 {IBS}
Ios 4 in_neg {IOS/2}
Rin 4 in_neg {RI}

*Middle stage: Gain, frequency, voltage limiting
Bgain 0 6 I={v(4,in_neg)*AVOL/1meg }
R1 6 0 1meg
CP1 6 0 {AVOL/(2*pi*1meg*BW)}


Vpos 9 0 {VOMP}
Dlimit_pos 6 9 d1

Vneg 10 0 {VOMN}
Dlimit_neg 10 6 d1

.model d1 d(n=0.1)

*Output stage: Buffer, output resistance
E2 7 0 6 0 1
Rout 7 out {RO}
.ends

* U2 subcircuit
.SUBCKT 3T_VIRTUAL_U2 in_pos in_neg out PARAMS: AVOL=500k BW=10Meg RI=10Meg RO=0 VOS=0 IBS=0 IOS=0 VOMP=15 VOMN=-15

* Input Stage: Rin, Ibias, Voffset
VOS in_pos 4 {VOS}
Ibias1 4 0 {IBS}
Ibias2 in_neg 0 {IBS}
Ios 4 in_neg {IOS/2}
Rin 4 in_neg {RI}

*Middle stage: Gain, frequency, voltage limiting
Bgain 0 6 I={v(4,in_neg)*AVOL/1meg }
R1 6 0 1meg
CP1 6 0 {AVOL/(2*pi*1meg*BW)}


Vpos 9 0 {VOMP}
Dlimit_pos 6 9 d1

Vneg 10 0 {VOMN}
Dlimit_neg 10 6 d1

.model d1 d(n=0.1)

*Output stage: Buffer, output resistance
E2 7 0 6 0 1
Rout 7 out {RO}
.ends

Errors and Warnings

Any error, warning or information messages appear below.

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Passa Baixa 2ยช ordem - VCVS
Schematic

The simulation to run. See Simulation types for more information.

Name

Title of graph. Edit as desired.

Start frequency

Hz

Frequency the sweep starts on.

Stop frequency

Hz

Frequency the sweep ends on.

Defines the distribution of the frequency range.

Points per decade

The number of points to be calculated for the simulation, relative to the Sweep configuration.

The type of vertical scale for the next simulation. After running the simulation, you can select a different vertical scale from the Item tab.

Start simulation

Mode

Threshold voltage levels.

Threshold voltage values used in the logic evaluation. See Digital Simulation for more information.

Output low

V

Output low voltage.

Maximum output voltage level to produce a low signal.

Input low threshold

V

Input low threshold voltage.

Maximum input voltage level for the signal to be considered low.

Input high threshold

V

Input high threshold voltage.

Minimum input voltage level for the signal to be considered high.

Output high

V

Output high voltage.

Minimum output voltage level to produce a high signal.

Width

Sheet width in grid squares.

Height

Sheet height in grid squares.

Grid

Toggles grid display.

Net Labels

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