*Power Electronics - Single Phase (Full-wave Uncontrolled Bridge Rectifier with Transformator with Center Tap)

Waiting for data

Signal	Value
Signal	Value

Cursor 1	Cursor 2	∆X	1/∆X	∆Y	∆Y (Phase)

Out of date
V	—
V	—
V_PP	—
V_RMS	—
V_AV	—
f_V	—
I	—
I	—
I_PP	—
I_RMS	—
I_AV	—
f_I	—
D	—

Out of date
V	—
V	—
V_PP	—
V_RMS	—
V_AV	—
f_V	—
I	—
I	—
I_PP	—
I_RMS	—
I_AV	—
f_I	—
D	—

Out of date
V	—
V	—
V_PP	—
V_RMS	—
V_AV	—
f_V	—
I	—
I	—
I_PP	—
I_RMS	—
I_AV	—
f_I	—
D	—

ID:

x10

x0.1

Sheet:1

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Circuit Details

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diode

rectifier

transformer

full-wave rectifier

uunej

rerectifier circuits

uncontrolled

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SPICE

SPICE Netlist

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** Power Electronics - Single Phase (Full-wave Uncontrolled Bridge Rectifier with Transformator with Center Tap) **
*
* Multisim Live SPICE netlist
*
*

* --- Circuit Topology ---

* Component: CSmooth
cCSmooth 8 0 0.0001

* Component: D1
dD1 4 6 DIODE_D1 AREA=1

* Component: D2
dD2 5 6 DIODE_D2 AREA=1

* Component: L1
lL1 2 9 0.000001

* Component: R1
rR1 6 7 10000 VIRTUAL_RESISTANCE_R1

* Component: S1
xS1 8 6 SPST_Switch_S1 Params: Ron=0.0001 Roff=100000000 State=1

* Component: S2
xS2 0 7 SPST_Switch_S2 Params: Ron=0.0001 Roff=100000000 State=1

* Component: S4
xS4 0 9 SPST_Switch_S4 Params: Ron=0.0001 Roff=100000000 State=0

* Component: T2
xT2 3 0 4 5 0 1P1S_TAPPED_T2

* Component: U1
xU1 1 3 FUSE_VIRTUAL_U1

* Component: UseInductor
xUseInductor 6 2 7 SPDT_Switch_UseInductor Params: Ron=0.0001 Roff=100000000 State=1

* Component: V1
vV1 1 0 dc 0 ac 1 0
+ distof1 0 0
+ distof2 0 0
+ sin ( 0 {220*1.414213562} 50 0 0 0 )

* --- Circuit Models ---

* D1 model
.model DIODE_D1 D( IS=1e-14 RS=0 N=1 BV=1e+30
+ TT=0 CJO=0 VJ=1 M=0.5 EG=1.11 XTI=3 KF=0 AF=1 FC=0.5 IBV=1e-10
+ IBVL=0 IKF=1e+30 ISR=0 NBV=1 NBVL=1 NR=2 TBV1=0 TBV2=0 TIKF=0
+ TRS1=0 TRS2=0
+ )

* D2 model
.model DIODE_D2 D( IS=1e-14 RS=0 N=1 BV=1e+30
+ TT=0 CJO=0 VJ=1 M=0.5 EG=1.11 XTI=3 KF=0 AF=1 FC=0.5 IBV=1e-10
+ IBVL=0 IKF=1e+30 ISR=0 NBV=1 NBVL=1 NR=2 TBV1=0 TBV2=0 TIKF=0
+ TRS1=0 TRS2=0
+ )

* R1 model
.model VIRTUAL_RESISTANCE_R1 r( )

* --- Subcircuits ---

* S1 subcircuit
.subckt SPST_Switch_S1 port1 port2 Params: Ron=1e-8 Roff=1e30 State=0
V2 state 0 DC {State}
R1 state 6 10
V1 6 0 DC 0
W0 port2 port1 V1 NC_contact
.model NC_contact ISWITCH (Ion=0.05 Ioff=0.025 Ron={Ron} Roff={Roff})
.ends

* S2 subcircuit
.subckt SPST_Switch_S2 port1 port2 Params: Ron=1e-8 Roff=1e30 State=0
V2 state 0 DC {State}
R1 state 6 10
V1 6 0 DC 0
W0 port2 port1 V1 NC_contact
.model NC_contact ISWITCH (Ion=0.05 Ioff=0.025 Ron={Ron} Roff={Roff})
.ends

* S4 subcircuit
.subckt SPST_Switch_S4 port1 port2 Params: Ron=1e-8 Roff=1e30 State=0
V2 state 0 DC {State}
R1 state 6 10
V1 6 0 DC 0
W0 port2 port1 V1 NC_contact
.model NC_contact ISWITCH (Ion=0.05 Ioff=0.025 Ron={Ron} Roff={Roff})
.ends

* T2 subcircuit
.SUBCKT 1P1S_TAPPED_T2 p1pos p1neg s1pos s1neg s1tap
.param PTurns = {10 * IF(PNegativePolarity < 0.5, 1, -1)}
.param PNegativePolarity = 0
.param STurns = {1 * IF(SNegativePolarity < 0.5, 1, -1)}
.param SNegativePolarity = 0
.param turns_per_coil = {STurns/2}
G1 p1pos p1neg value={-1/PTurns*(turns_per_coil*I(Es1) + turns_per_coil*I(Es2))}
Es1 s1pos s1tap value={V(p1pos,p1neg)*turns_per_coil/PTurns}
Es2 s1tap s1neg value={V(p1pos,p1neg)*turns_per_coil/PTurns}
.ENDS

* U1 subcircuit
.subckt FUSE_VIRTUAL_U1 port1 port2

** Maximum current as defined by the user
.param Imax = 6

** resistance of the fuse when conducting current
.param fuseResistance = 1e-4

** resistance of the fuse after burning out
.param blownResistance = 10e6

** blown signal appears on node blown. 5V = blown, 0 = not
Rdummy blown 0 1000000

** Constant digital high to feed as input to latch
aU2 dU1.DATA d_constsource_U2
.model d_constsource_U2 d_constsource(state=1)

**D-latch to latch state
aU1 dU1.DATA
+ dU1.EN
+ U1_OPEN_SET
+ U1_OPEN_RESET
+ dU1.Q
+ U1_OPEN_notQ D_LATCH

** Output of latch onto node `blown` through DAC
xU1.Q dU1.Q blown TIL_DRV

** Input node `trigger` to latch ENABLE through ADC
xU1.CLK trigger dU1.EN TIL_RCV

** If over blown voltage, trigger DLATCH U1 enable
E2 trigger 0 Value = { if( abs(I(V_Isense)) > Imax & Time > 0, 5, 0) }

** Current sensor
V_Isense port1 lampSense 0

** model of the fuse as a G source so we can change the resistance on the fly
G_Lamp lampSense port2 value = { if( V(blown) < 2.5, V(port1, port2) / fuseResistance, V(port1, port2) / blownResistance )}

.subckt TIL_DRV 1 2
* TIL Driver Model 1= D/A input, 2 = out
aDACin1 [1] [2] aDAC
.model aDAC dac_bridge (out_low = 0 out_high = 5 out_undef = 2.5)
.ends

.subckt TIL_RCV 1 2
* TIL Receiver Model 1 = input, 2 = A/D out
aADCin1 [1] [2] ADC
.model ADC adc_bridge (in_low = 2.5 in_high = 2.5)
.ends

.model D_LATCH d_dlatch (data_delay = 1n enable_delay = 1n
+ set_delay = 1n reset_delay = 1n
+ ic = 0 rise_delay = 1n fall_delay = 1n)

.ends

* UseInductor subcircuit
.subckt SPDT_Switch_UseInductor port1 port2 port3 Params: Ron=1e-8 Roff=1e30 State=0
V2 state 0 DC {State}
R1 state 6 10
V1 6 0 DC 0
W0 port2 port1 V1 NC_contact
W1 port2 port3 V1 NO_contact
.MODEL NO_contact ISWITCH (ION=0.05 IOFF=0.025 RON={Ron} ROFF={Roff})
.MODEL NC_contact ISWITCH (ION=0.05 IOFF=0.025 RON={Roff} ROFF={Ron})
.ends

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Item

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Section

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Type

Rise time

Time it takes for signal to transition from low to high.

With non-zero rise time, the signal converts to an analog signal from a digital signal.

Fall time

Time it takes for signal to transition from high to low.

With non-zero fall time, the signal converts to an analog signal from a digital signal.

Use document settings

Use logic levels settings from Document tab.

Threshold voltage levels.

Threshold voltage values used in the logic evaluation. See Digital Simulation for more information.

Output low

Output low voltage.

Maximum output voltage level to produce a low signal.

Input low threshold

Input low threshold voltage.

Maximum input voltage level for the signal to be considered low.

Input high threshold

Input high threshold voltage.

Minimum input voltage level for the signal to be considered high.

Output high

Output high voltage.

Minimum output voltage level to produce a high signal.

Type Probe

Select desired function.

Function

Use document settings

Use logic levels settings from Document tab.

Threshold voltage levels.

Threshold voltage values used in the logic evaluation. See Digital Simulation for more information.

Output low

Output low voltage.

Maximum output voltage level to produce a low signal.

Input low threshold

Input low threshold voltage.

Maximum input voltage level for the signal to be considered low.

Input high threshold

Input high threshold voltage.

Minimum input voltage level for the signal to be considered high.

Output high

Output high voltage.

Minimum output voltage level to produce a high signal.

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Name Power Electronics - Single Phase (Full-wave Uncontrolled Bridge Rectifier with Transformator with Center Tap)

Type Schematic

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Name

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End time

Time at which the simulation stops. Does not include pauses. Simulation does not occur in real time.

Start simulation

RELTOL

Relative error tolerance. A simulation wide accuracy control used to establish convergence.

VNTOL

Absolute voltage error tolerance. Defines the minimum value for voltage where it may still be considered accurate.

ABSTOL

Absolute current error tolerance. Defines the minimum value for current where it may still be considered accurate.

ITL1

DC iteration limit. Number of iterative passes done on DC circuit equations in attempt to reach convergence in simulation.

ITL4

Upper iteration limit. Number of iterative passes done per time point, on Transient circuit equations in attempt to reach convergence in simulation.

Integration method. The numerical integration method used in transient analysis.

Temp

℃

Operating temperature. The temperature at which the entire circuit will be simulated.

Insert shunt resistance

Inserts a resistance of RSHUNT from every analog node to ground. Will aid in convergence, but alter the behavior of the circuit.

RSHUNT

Shunt resistance. This eliminates singular matrix errors that result from a lack of a DC path to ground.

Reset to default

Threshold voltage levels.

Threshold voltage values used in the logic evaluation. See Digital Simulation for more information.

Output low

Output low voltage.

Maximum output voltage level to produce a low signal.

Input low threshold

Input low threshold voltage.

Maximum input voltage level for the signal to be considered low.

Input high threshold

Input high threshold voltage.

Minimum input voltage level for the signal to be considered high.

Output high

Output high voltage.

Minimum output voltage level to produce a high signal.

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Power Electronics - Single Phase (Full-wave Uncontrolled Bridge Rectifier with Transformator with Center Tap)