*60 Second Timer

Waiting for data

Signal	Value
Signal	Value

Cursor 1	Cursor 2	∆X	1/∆X	∆Y	∆Y (Phase)

ID:

x10

x0.1

Sheet:1

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SPICE

SPICE Netlist

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** 60 Second Timer **
*
* Multisim Live SPICE netlist
*
*

* --- Circuit Topology ---

* Component: Start
aStart 34 Digital_Source_Start

* Component: U1
xU1 18 23 22 24 21 20 19 0 7_SEGMENT_CC_U1

* Component: U10
aU10 [34 35 25] 26 Digital_OR3_U10

* Component: U11
xU11 27 25 U11_NC_SET 34 30 27 Digital_DFlipFlop_U11 PARAMS: Negative_Edge_Clock=0 Negative_SET_RESET=0 Rise_delay=1e-9 Fall_delay=1e-9 Clk_delay=1e-9 Set_delay=1e-9 Reset_delay=1e-9 Ic=0

* Component: U12
xU12 28 27 U12_NC_SET 34 31 28 Digital_DFlipFlop_U12 PARAMS: Negative_Edge_Clock=0 Negative_SET_RESET=0 Rise_delay=1e-9 Fall_delay=1e-9 Clk_delay=1e-9 Set_delay=1e-9 Reset_delay=1e-9 Ic=0

* Component: U13
xU13 29 28 U13_NC_SET 34 32 29 Digital_DFlipFlop_U13 PARAMS: Negative_Edge_Clock=0 Negative_SET_RESET=0 Rise_delay=1e-9 Fall_delay=1e-9 Clk_delay=1e-9 Set_delay=1e-9 Reset_delay=1e-9 Ic=0

* Component: U14
aU14 [32 31 27] 35 Digital_AND3_U14

* Component: U2
xU2 9 10 15 14 13 12 11 0 7_SEGMENT_CC_U2

* Component: U3
xU3 30 31 32 bridgeU3!D bridgeU3!~LT bridgeU3!~RBI bridgeU3!~BI/RBO bridgeU3!OA bridgeU3!OD bridgeU3!OE bridgeU3!OF bridgeU3!OC bridgeU3!OB bridgeU3!OG 74LS48_U3 PARAMS: Rise_delay=1e-7 Fall_delay=1e-7

xbridgeU3!D bridgeU3!D 0 REAL_CUSTOM_ADC PARAMS: lowV=0 maxLowV=0.8 unknownV=1 minHighV=2 highV=3.3 riseT=0 fallT=0

xbridgeU3!~LT bridgeU3!~LT 33 REAL_CUSTOM_ADC PARAMS: lowV=0 maxLowV=0.8 unknownV=1 minHighV=2 highV=3.3 riseT=0 fallT=0

xbridgeU3!~RBI bridgeU3!~RBI 33 REAL_CUSTOM_ADC PARAMS: lowV=0 maxLowV=0.8 unknownV=1 minHighV=2 highV=3.3 riseT=0 fallT=0

xbridgeU3!~BI/RBO bridgeU3!~BI/RBO 33 REAL_CUSTOM_ADC PARAMS: lowV=0 maxLowV=0.8 unknownV=1 minHighV=2 highV=3.3 riseT=0 fallT=0

xbridgeU3!OA bridgeU3!OA 18 REAL_CUSTOM_DAC PARAMS: lowV=0 maxLowV=0.8 unknownV=1 minHighV=2 highV=3.3 riseT=0 fallT=0

xbridgeU3!OD bridgeU3!OD 24 REAL_CUSTOM_DAC PARAMS: lowV=0 maxLowV=0.8 unknownV=1 minHighV=2 highV=3.3 riseT=0 fallT=0

xbridgeU3!OE bridgeU3!OE 21 REAL_CUSTOM_DAC PARAMS: lowV=0 maxLowV=0.8 unknownV=1 minHighV=2 highV=3.3 riseT=0 fallT=0

xbridgeU3!OF bridgeU3!OF 20 REAL_CUSTOM_DAC PARAMS: lowV=0 maxLowV=0.8 unknownV=1 minHighV=2 highV=3.3 riseT=0 fallT=0

xbridgeU3!OC bridgeU3!OC 22 REAL_CUSTOM_DAC PARAMS: lowV=0 maxLowV=0.8 unknownV=1 minHighV=2 highV=3.3 riseT=0 fallT=0

xbridgeU3!OB bridgeU3!OB 23 REAL_CUSTOM_DAC PARAMS: lowV=0 maxLowV=0.8 unknownV=1 minHighV=2 highV=3.3 riseT=0 fallT=0

xbridgeU3!OG bridgeU3!OG 19 REAL_CUSTOM_DAC PARAMS: lowV=0 maxLowV=0.8 unknownV=1 minHighV=2 highV=3.3 riseT=0 fallT=0

* Component: U4
xU4 2 7 8 16 bridgeU4!~LT bridgeU4!~RBI bridgeU4!~BI/RBO bridgeU4!OA bridgeU4!OD bridgeU4!OE bridgeU4!OF bridgeU4!OC bridgeU4!OB bridgeU4!OG 74LS48_U4 PARAMS: Rise_delay=1e-7 Fall_delay=1e-7

xbridgeU4!~LT bridgeU4!~LT 17 REAL_CUSTOM_ADC PARAMS: lowV=0 maxLowV=0.8 unknownV=1 minHighV=2 highV=3.3 riseT=0 fallT=0

xbridgeU4!~RBI bridgeU4!~RBI 17 REAL_CUSTOM_ADC PARAMS: lowV=0 maxLowV=0.8 unknownV=1 minHighV=2 highV=3.3 riseT=0 fallT=0

xbridgeU4!~BI/RBO bridgeU4!~BI/RBO 17 REAL_CUSTOM_ADC PARAMS: lowV=0 maxLowV=0.8 unknownV=1 minHighV=2 highV=3.3 riseT=0 fallT=0

xbridgeU4!OA bridgeU4!OA 9 REAL_CUSTOM_DAC PARAMS: lowV=0 maxLowV=0.8 unknownV=1 minHighV=2 highV=3.3 riseT=0 fallT=0

xbridgeU4!OD bridgeU4!OD 14 REAL_CUSTOM_DAC PARAMS: lowV=0 maxLowV=0.8 unknownV=1 minHighV=2 highV=3.3 riseT=0 fallT=0

xbridgeU4!OE bridgeU4!OE 13 REAL_CUSTOM_DAC PARAMS: lowV=0 maxLowV=0.8 unknownV=1 minHighV=2 highV=3.3 riseT=0 fallT=0

xbridgeU4!OF bridgeU4!OF 12 REAL_CUSTOM_DAC PARAMS: lowV=0 maxLowV=0.8 unknownV=1 minHighV=2 highV=3.3 riseT=0 fallT=0

xbridgeU4!OC bridgeU4!OC 15 REAL_CUSTOM_DAC PARAMS: lowV=0 maxLowV=0.8 unknownV=1 minHighV=2 highV=3.3 riseT=0 fallT=0

xbridgeU4!OB bridgeU4!OB 10 REAL_CUSTOM_DAC PARAMS: lowV=0 maxLowV=0.8 unknownV=1 minHighV=2 highV=3.3 riseT=0 fallT=0

xbridgeU4!OG bridgeU4!OG 11 REAL_CUSTOM_DAC PARAMS: lowV=0 maxLowV=0.8 unknownV=1 minHighV=2 highV=3.3 riseT=0 fallT=0

* Component: U5
xU5 3 bridgeU5!CLK U5_NC_SET 26 2 3 Digital_DFlipFlop_U5 PARAMS: Negative_Edge_Clock=0 Negative_SET_RESET=0 Rise_delay=1e-9 Fall_delay=1e-9 Clk_delay=1e-9 Set_delay=1e-9 Reset_delay=1e-9 Ic=0

xbridgeU5!CLK bridgeU5!CLK 1 REAL_CUSTOM_ADC PARAMS: lowV=0 maxLowV=0.8 unknownV=1 minHighV=2 highV=3.3 riseT=0 fallT=0

* Component: U6
xU6 4 3 U6_NC_SET 26 7 4 Digital_DFlipFlop_U6 PARAMS: Negative_Edge_Clock=0 Negative_SET_RESET=0 Rise_delay=1e-9 Fall_delay=1e-9 Clk_delay=1e-9 Set_delay=1e-9 Reset_delay=1e-9 Ic=0

* Component: U7
xU7 5 4 U7_NC_SET 26 8 5 Digital_DFlipFlop_U7 PARAMS: Negative_Edge_Clock=0 Negative_SET_RESET=0 Rise_delay=1e-9 Fall_delay=1e-9 Clk_delay=1e-9 Set_delay=1e-9 Reset_delay=1e-9 Ic=0

* Component: U8
xU8 6 5 U8_NC_SET 26 16 6 Digital_DFlipFlop_U8 PARAMS: Negative_Edge_Clock=0 Negative_SET_RESET=0 Rise_delay=1e-9 Fall_delay=1e-9 Clk_delay=1e-9 Set_delay=1e-9 Reset_delay=1e-9 Ic=0

* Component: U9
aU9 [16 5 7 3] 25 Digital_AND4_U9

* Component: V1
vV1 1 0
+ pulse( 0 5 0 1e-9 1e-9
+ { 50 * 0.01 / 0.0005 }
+ { 1/0.0005 } )

* Component: V2
vV2 17 0 dc 5 ac 0 0
+ distof1 0 0
+ distof2 0 0

* Component: V3
vV3 33 0 dc 5 ac 0 0
+ distof1 0 0
+ distof2 0 0

* --- Circuit Models ---

* Start model
.model Digital_Source_Start d_constsource(State=0)

* U10 model
.model Digital_OR3_U10 d_or (rise_delay=1e-9 fall_delay=1e-9)

* U14 model
.model Digital_AND3_U14 d_and (rise_delay=1e-9 fall_delay=1e-9)

* U9 model
.model Digital_AND4_U9 d_and (rise_delay=1e-9 fall_delay=1e-9)

* --- Subcircuits ---

* U1 subcircuit
.subckt 7_SEGMENT_CC_U1 A1 A2 A3 A4 A5 A6 A7 K

dd1 A1 0vNode1 ledDiodeModel
Vsense1 0vNode1 K DC 0
* Interactive sense node
b1 lit1 0 v = { if (i(Vsense1) < 0, 0, if( i(Vsense1) > 0.02, 1, { i(Vsense1) / 0.02 })) }

dd2 A2 0vNode2 ledDiodeModel
Vsense2 0vNode2 K DC 0
* Interactive sense node
b2 lit2 0 v = { if (i(Vsense2) < 0, 0, if( i(Vsense2) > 0.02, 1, { i(Vsense2) / 0.02 })) }

dd3 A3 0vNode3 ledDiodeModel
Vsense3 0vNode3 K DC 0
* Interactive sense node
b3 lit3 0 v = { if (i(Vsense3) < 0, 0, if( i(Vsense3) > 0.02, 1, { i(Vsense3) / 0.02 })) }

dd4 A4 0vNode4 ledDiodeModel
Vsense4 0vNode4 K DC 0
* Interactive sense node
b4 lit4 0 v = { if (i(Vsense4) < 0, 0, if( i(Vsense4) > 0.02, 1, { i(Vsense4) / 0.02 })) }

dd5 A5 0vNode5 ledDiodeModel
Vsense5 0vNode5 K DC 0
* Interactive sense node
b5 lit5 0 v = { if (i(Vsense5) < 0, 0, if( i(Vsense5) > 0.02, 1, { i(Vsense5) / 0.02 })) }

dd6 A6 0vNode6 ledDiodeModel
Vsense6 0vNode6 K DC 0
* Interactive sense node
b6 lit6 0 v = { if (i(Vsense6) < 0, 0, if( i(Vsense6) > 0.02, 1, { i(Vsense6) / 0.02 })) }

dd7 A7 0vNode7 ledDiodeModel
Vsense7 0vNode7 K DC 0
* Interactive sense node
b7 lit7 0 v = { if (i(Vsense7) < 0, 0, if( i(Vsense7) > 0.02, 1, { i(Vsense7) / 0.02 })) }

.model ledDiodeModel D( IS=1e-14 N=1 RS=0 IBV=1e-10 BV=1e+30 CJO=0 M=0.5 VJ=1 )
.ends

* U11 subcircuit
.subckt Digital_DFlipFlop_U11 1 2 3 4 5 6 PARAMS: Negative_Edge_Clock=0 Negative_SET_RESET=0 Clk_delay=1n Set_delay=1n Reset_delay=1n Ic=0 Rise_delay=1n Fall_delay=1n
*PIN MAPPING: D Q ~Q RESET CLK SET
* 1 5 6 4 2 3
*MODELS USED
aDG1 neg_SR Digital_SourceSR
aDG2 neg_clk Digital_SourceCLK
Axor1 [3 neg_SR] set xor
Axor2 [2 neg_clk] clk xor
Axor3 [4 neg_SR] reset xor
Ajkff 1 clk set reset 5 6 D_FF

.model Digital_SourceCLK d_constsource(State={Negative_Edge_Clock})
.model Digital_SourceSR d_constsource(State={Negative_SET_RESET})
.model xor d_xor
.MODEL D_FF d_dff (clk_delay={Clk_delay} set_delay={Set_delay} reset_delay={Reset_delay} ic={Ic} rise_delay={Rise_delay} fall_delay={Fall_delay})
.ENDS

* U12 subcircuit
.subckt Digital_DFlipFlop_U12 1 2 3 4 5 6 PARAMS: Negative_Edge_Clock=0 Negative_SET_RESET=0 Clk_delay=1n Set_delay=1n Reset_delay=1n Ic=0 Rise_delay=1n Fall_delay=1n
*PIN MAPPING: D Q ~Q RESET CLK SET
* 1 5 6 4 2 3
*MODELS USED
aDG1 neg_SR Digital_SourceSR
aDG2 neg_clk Digital_SourceCLK
Axor1 [3 neg_SR] set xor
Axor2 [2 neg_clk] clk xor
Axor3 [4 neg_SR] reset xor
Ajkff 1 clk set reset 5 6 D_FF

.model Digital_SourceCLK d_constsource(State={Negative_Edge_Clock})
.model Digital_SourceSR d_constsource(State={Negative_SET_RESET})
.model xor d_xor
.MODEL D_FF d_dff (clk_delay={Clk_delay} set_delay={Set_delay} reset_delay={Reset_delay} ic={Ic} rise_delay={Rise_delay} fall_delay={Fall_delay})
.ENDS

* U13 subcircuit
.subckt Digital_DFlipFlop_U13 1 2 3 4 5 6 PARAMS: Negative_Edge_Clock=0 Negative_SET_RESET=0 Clk_delay=1n Set_delay=1n Reset_delay=1n Ic=0 Rise_delay=1n Fall_delay=1n
*PIN MAPPING: D Q ~Q RESET CLK SET
* 1 5 6 4 2 3
*MODELS USED
aDG1 neg_SR Digital_SourceSR
aDG2 neg_clk Digital_SourceCLK
Axor1 [3 neg_SR] set xor
Axor2 [2 neg_clk] clk xor
Axor3 [4 neg_SR] reset xor
Ajkff 1 clk set reset 5 6 D_FF

.model Digital_SourceCLK d_constsource(State={Negative_Edge_Clock})
.model Digital_SourceSR d_constsource(State={Negative_SET_RESET})
.model xor d_xor
.MODEL D_FF d_dff (clk_delay={Clk_delay} set_delay={Set_delay} reset_delay={Reset_delay} ic={Ic} rise_delay={Rise_delay} fall_delay={Fall_delay})
.ENDS

* U2 subcircuit
.subckt 7_SEGMENT_CC_U2 A1 A2 A3 A4 A5 A6 A7 K

dd1 A1 0vNode1 ledDiodeModel
Vsense1 0vNode1 K DC 0
* Interactive sense node
b1 lit1 0 v = { if (i(Vsense1) < 0, 0, if( i(Vsense1) > 0.02, 1, { i(Vsense1) / 0.02 })) }

dd2 A2 0vNode2 ledDiodeModel
Vsense2 0vNode2 K DC 0
* Interactive sense node
b2 lit2 0 v = { if (i(Vsense2) < 0, 0, if( i(Vsense2) > 0.02, 1, { i(Vsense2) / 0.02 })) }

dd3 A3 0vNode3 ledDiodeModel
Vsense3 0vNode3 K DC 0
* Interactive sense node
b3 lit3 0 v = { if (i(Vsense3) < 0, 0, if( i(Vsense3) > 0.02, 1, { i(Vsense3) / 0.02 })) }

dd4 A4 0vNode4 ledDiodeModel
Vsense4 0vNode4 K DC 0
* Interactive sense node
b4 lit4 0 v = { if (i(Vsense4) < 0, 0, if( i(Vsense4) > 0.02, 1, { i(Vsense4) / 0.02 })) }

dd5 A5 0vNode5 ledDiodeModel
Vsense5 0vNode5 K DC 0
* Interactive sense node
b5 lit5 0 v = { if (i(Vsense5) < 0, 0, if( i(Vsense5) > 0.02, 1, { i(Vsense5) / 0.02 })) }

dd6 A6 0vNode6 ledDiodeModel
Vsense6 0vNode6 K DC 0
* Interactive sense node
b6 lit6 0 v = { if (i(Vsense6) < 0, 0, if( i(Vsense6) > 0.02, 1, { i(Vsense6) / 0.02 })) }

dd7 A7 0vNode7 ledDiodeModel
Vsense7 0vNode7 K DC 0
* Interactive sense node
b7 lit7 0 v = { if (i(Vsense7) < 0, 0, if( i(Vsense7) > 0.02, 1, { i(Vsense7) / 0.02 })) }

.model ledDiodeModel D( IS=1e-14 N=1 RS=0 IBV=1e-10 BV=1e+30 CJO=0 M=0.5 VJ=1 )
.ends

* U3 subcircuit
**********************
*74LS48 DECODER/DRIVER BCD-7 SEGMENT WITH
*2k PULL-UPS OUTPUTS
***
.subckt 74LS48_U3 ina inb inc ind ltb rbib bib/rbob a d e f c b g PARAMS: Rise_delay=100n Fall_delay=100n
*FAMILY TTLin TTLin TTLin TTLin TTLin TTLin TTLin
*TTLout TTLout TTLout TTLout TTLout TTLout TTLout
*pinout N 7 1 2 6 13 10 9 15 11 12 14 3 5 4:VCC=16 GND=8
*pinout J 7 1 2 6 13 10 9 15 11 12 14 3 5 4:VCC=16 GND=8
*pinout D 7 1 2 6 13 10 9 15 11 12 14 3 5 4:VCC=16 GND=8

ainv1 rbib rbi inv

ananda1 [ina ltb] a1 nand
anandb1 [inb ltb] b1 nand
anandc1 [inc ltb] c1 nand
anandd1 [ind ind] d1 nand

ananda2 [a1 bib/rbob] a2 nand
anandb2 [b1 bib/rbob] b2 nand
anandc2 [c1 bib/rbob] c2 nand
anandd2 [d1 bib/rbob] d2 nand

anand6 [ltb rbi d1 c1 b1 a1] nandopenc nand

aopenc1 nandopenc bib/rbob open_c

aand1a [b2 d2] x1 and
aand2a [a1 c2] x2 and
aand3a [a2 b1 c1 d1] x3 and
aor1 [x1 x2 x3] ai or

aand1b [b2 d2] x4 and
aand2b [a2 b1 c2] x5 and
aand3b [a1 b2 c2] x6 and
aor2 [x4 x5 x6] bi or

aand1c [c2 d2] x7 and
aand2c [a1 b2 c1] x8 and
aor3 [x7 x8] ci or

aand1d [a2 b1 c1] x9 and
aand2d [a1 b1 c2] xa and
aand3d [a2 b2 c2] xb and
aor4 [x9 xa xb] di or

aand1e [b1 c2] xc and
aor5 [xc a2] ei or

aand1f [a2 b2] xd and
aand2f [b2 c1] xe and
aand3f [a2 c1 d1] xf and
aor6 [xd xe xf] fi or

aand1g [a2 b2 c2] xg and
aand2g [b1 c1 d1 ltb] xh and
aor7 [xg xh] gi or

ah h high

aand1 [ai h] a nand
aand2 [bi h] b nand
aand3 [ci h] c nand
aand4 [di h] d nand
aand5 [ei h] e nand
aand6 [fi h] f nand
aand7 [gi h] g nand

.model inv d_inverter
.model nand d_nand
.model or d_or(rise_delay={Rise_delay} fall_delay={Fall_delay})
.model and d_and
.model open_c d_open_c
.model high d_pullup(load=2k)

.ends

* U4 subcircuit
**********************
*74LS48 DECODER/DRIVER BCD-7 SEGMENT WITH
*2k PULL-UPS OUTPUTS
***
.subckt 74LS48_U4 ina inb inc ind ltb rbib bib/rbob a d e f c b g PARAMS: Rise_delay=100n Fall_delay=100n
*FAMILY TTLin TTLin TTLin TTLin TTLin TTLin TTLin
*TTLout TTLout TTLout TTLout TTLout TTLout TTLout
*pinout N 7 1 2 6 13 10 9 15 11 12 14 3 5 4:VCC=16 GND=8
*pinout J 7 1 2 6 13 10 9 15 11 12 14 3 5 4:VCC=16 GND=8
*pinout D 7 1 2 6 13 10 9 15 11 12 14 3 5 4:VCC=16 GND=8

ainv1 rbib rbi inv

ananda1 [ina ltb] a1 nand
anandb1 [inb ltb] b1 nand
anandc1 [inc ltb] c1 nand
anandd1 [ind ind] d1 nand

ananda2 [a1 bib/rbob] a2 nand
anandb2 [b1 bib/rbob] b2 nand
anandc2 [c1 bib/rbob] c2 nand
anandd2 [d1 bib/rbob] d2 nand

anand6 [ltb rbi d1 c1 b1 a1] nandopenc nand

aopenc1 nandopenc bib/rbob open_c

aand1a [b2 d2] x1 and
aand2a [a1 c2] x2 and
aand3a [a2 b1 c1 d1] x3 and
aor1 [x1 x2 x3] ai or

aand1b [b2 d2] x4 and
aand2b [a2 b1 c2] x5 and
aand3b [a1 b2 c2] x6 and
aor2 [x4 x5 x6] bi or

aand1c [c2 d2] x7 and
aand2c [a1 b2 c1] x8 and
aor3 [x7 x8] ci or

aand1d [a2 b1 c1] x9 and
aand2d [a1 b1 c2] xa and
aand3d [a2 b2 c2] xb and
aor4 [x9 xa xb] di or

aand1e [b1 c2] xc and
aor5 [xc a2] ei or

aand1f [a2 b2] xd and
aand2f [b2 c1] xe and
aand3f [a2 c1 d1] xf and
aor6 [xd xe xf] fi or

aand1g [a2 b2 c2] xg and
aand2g [b1 c1 d1 ltb] xh and
aor7 [xg xh] gi or

ah h high

aand1 [ai h] a nand
aand2 [bi h] b nand
aand3 [ci h] c nand
aand4 [di h] d nand
aand5 [ei h] e nand
aand6 [fi h] f nand
aand7 [gi h] g nand

.model inv d_inverter
.model nand d_nand
.model or d_or(rise_delay={Rise_delay} fall_delay={Fall_delay})
.model and d_and
.model open_c d_open_c
.model high d_pullup(load=2k)

.ends

* U5 subcircuit
.subckt Digital_DFlipFlop_U5 1 2 3 4 5 6 PARAMS: Negative_Edge_Clock=0 Negative_SET_RESET=0 Clk_delay=1n Set_delay=1n Reset_delay=1n Ic=0 Rise_delay=1n Fall_delay=1n
*PIN MAPPING: D Q ~Q RESET CLK SET
* 1 5 6 4 2 3
*MODELS USED
aDG1 neg_SR Digital_SourceSR
aDG2 neg_clk Digital_SourceCLK
Axor1 [3 neg_SR] set xor
Axor2 [2 neg_clk] clk xor
Axor3 [4 neg_SR] reset xor
Ajkff 1 clk set reset 5 6 D_FF

.model Digital_SourceCLK d_constsource(State={Negative_Edge_Clock})
.model Digital_SourceSR d_constsource(State={Negative_SET_RESET})
.model xor d_xor
.MODEL D_FF d_dff (clk_delay={Clk_delay} set_delay={Set_delay} reset_delay={Reset_delay} ic={Ic} rise_delay={Rise_delay} fall_delay={Fall_delay})
.ENDS

* U6 subcircuit
.subckt Digital_DFlipFlop_U6 1 2 3 4 5 6 PARAMS: Negative_Edge_Clock=0 Negative_SET_RESET=0 Clk_delay=1n Set_delay=1n Reset_delay=1n Ic=0 Rise_delay=1n Fall_delay=1n
*PIN MAPPING: D Q ~Q RESET CLK SET
* 1 5 6 4 2 3
*MODELS USED
aDG1 neg_SR Digital_SourceSR
aDG2 neg_clk Digital_SourceCLK
Axor1 [3 neg_SR] set xor
Axor2 [2 neg_clk] clk xor
Axor3 [4 neg_SR] reset xor
Ajkff 1 clk set reset 5 6 D_FF

.model Digital_SourceCLK d_constsource(State={Negative_Edge_Clock})
.model Digital_SourceSR d_constsource(State={Negative_SET_RESET})
.model xor d_xor
.MODEL D_FF d_dff (clk_delay={Clk_delay} set_delay={Set_delay} reset_delay={Reset_delay} ic={Ic} rise_delay={Rise_delay} fall_delay={Fall_delay})
.ENDS

* U7 subcircuit
.subckt Digital_DFlipFlop_U7 1 2 3 4 5 6 PARAMS: Negative_Edge_Clock=0 Negative_SET_RESET=0 Clk_delay=1n Set_delay=1n Reset_delay=1n Ic=0 Rise_delay=1n Fall_delay=1n
*PIN MAPPING: D Q ~Q RESET CLK SET
* 1 5 6 4 2 3
*MODELS USED
aDG1 neg_SR Digital_SourceSR
aDG2 neg_clk Digital_SourceCLK
Axor1 [3 neg_SR] set xor
Axor2 [2 neg_clk] clk xor
Axor3 [4 neg_SR] reset xor
Ajkff 1 clk set reset 5 6 D_FF

.model Digital_SourceCLK d_constsource(State={Negative_Edge_Clock})
.model Digital_SourceSR d_constsource(State={Negative_SET_RESET})
.model xor d_xor
.MODEL D_FF d_dff (clk_delay={Clk_delay} set_delay={Set_delay} reset_delay={Reset_delay} ic={Ic} rise_delay={Rise_delay} fall_delay={Fall_delay})
.ENDS

* U8 subcircuit
.subckt Digital_DFlipFlop_U8 1 2 3 4 5 6 PARAMS: Negative_Edge_Clock=0 Negative_SET_RESET=0 Clk_delay=1n Set_delay=1n Reset_delay=1n Ic=0 Rise_delay=1n Fall_delay=1n
*PIN MAPPING: D Q ~Q RESET CLK SET
* 1 5 6 4 2 3
*MODELS USED
aDG1 neg_SR Digital_SourceSR
aDG2 neg_clk Digital_SourceCLK
Axor1 [3 neg_SR] set xor
Axor2 [2 neg_clk] clk xor
Axor3 [4 neg_SR] reset xor
Ajkff 1 clk set reset 5 6 D_FF

.model Digital_SourceCLK d_constsource(State={Negative_Edge_Clock})
.model Digital_SourceSR d_constsource(State={Negative_SET_RESET})
.model xor d_xor
.MODEL D_FF d_dff (clk_delay={Clk_delay} set_delay={Set_delay} reset_delay={Reset_delay} ic={Ic} rise_delay={Rise_delay} fall_delay={Fall_delay})
.ENDS

* --- Pin bridge models

.SUBCKT REAL_CUSTOM_ADC 1 2 PARAMS: lowV=0 maxLowV=0.8 unknownV=1.0 minHighV=2.0 highV=5.0 riseT=0 fallT=0
* Ideal Receiver Model 1 = input, 2 = A/D out
aADCin1 [2] [1] ADC
.MODEL ADC adc_bridge (in_low = {maxLowV} in_high = {minHighV})
.ENDS

.SUBCKT REAL_CUSTOM_DAC 1 2 PARAMS: lowV=0 maxLowV=0.8 unknownV=1.0 minHighV=2.0 highV=5.0 riseT=0 fallT=0
* Ideal Driver Model 1 = A/D out, 2 = input
aDACin1 [1] [2] aDAC
.MODEL aDAC dac_bridge (out_low = {lowV} out_high = {highV} out_undef = {unknownV} t_rise = {max(riseT,1e-9)} t_fall = {max(fallT,1e-9)})
.ENDS

Errors and Warnings

Any error, warning or information messages appear below.