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85V60Hz0°V1120VX11.15μFC11kΩR1250kΩ1.00%R2320MAC08MT1GD2D3D457PR1PR2 V V
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x10
x0.1
Sheet:1
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** Dimmer exemplo 5_1 Hart **
*
* Multisim Live SPICE netlist
*
*

* --- Circuit Topology ---

* Component: C1
cC1 2 0 1.5e-7

* Component: D2
xD2 3 5 0 MAC08MT1/ON_D2

* Component: D3
dD3 7 5 DIODE_D3 AREA=1

* Component: D4
dD4 5 7 DIODE_D4 AREA=1

* Component: R1
rR1 2 7 1000 VIRTUAL_RESISTANCE_R1

* Component: R2
xR2 2 3 3 Potentiometer_R2 PARAMS: res=250000 posPercent=1

* Component: V1
vV1 1 0 dc 0 ac 1 0
+ distof1 0 0
+ distof2 0 0
+ sin ( 0 85 60 0 0 0 )

* Component: X1
xX1 1 3 VIR_LAMP_X1


* --- Circuit Models ---

* D3 model
.model DIODE_D3 D( IS=1e-14 RS=0 N=1 BV=1e+30
+ TT=0 CJO=0 VJ=28 M=0.5 EG=1.11 XTI=3 KF=0 AF=1 FC=0.5 IBV=1e-10
+ IBVL=0 IKF=1e+30 ISR=0 NBV=1 NBVL=1 NR=2 TBV1=0 TBV2=0 TIKF=0
+ TRS1=0 TRS2=0
+ )

* D4 model
.model DIODE_D4 D( IS=1e-14 RS=0 N=1 BV=1e+30
+ TT=0 CJO=0 VJ=28 M=0.5 EG=1.11 XTI=3 KF=0 AF=1 FC=0.5 IBV=1e-10
+ IBVL=0 IKF=1e+30 ISR=0 NBV=1 NBVL=1 NR=2 TBV1=0 TBV2=0 TIKF=0
+ TRS1=0 TRS2=0
+ )

* R1 model
.model VIRTUAL_RESISTANCE_R1 r( )


* --- Subcircuits ---

* D2 subcircuit
.subckt MAC08MT1/ON_D2 MT2 gate MT1 PARAMS:
+ Vdrm=600v Idrm=10u
+ Ih=5ma dVdt=10e6
+ Igt=10ma Vgt=2.0v
+ Vtm=1.9v Itm=1.1
+ Ton=1.5u
* Where:
* Vdrm => Forward breakover voltage
* Idrm => Peak blocking current
* Ih => Holding current [MT2(+)]
* dVdt => Critical value for dV/dt triggering
* Igt => Gate trigger current [MT2(+),G(-)]
* Vgt => Gate trigger voltage [MT2(+),G(-)]
* Vtm => On-state voltage
* Itm => On-state current
* Ton => Turn-on time
* Main conduction path
Striac MT2 MT20 cntrol 0 Vswitch ; controlled switch
Dak1 MT20 MT22 Dak OFF ; triac is initially off
VIak MT22 MT1 ; current sensor
Striacr MT2 MT23 cntrolr 0 Vswitch ; controlled switch
Dka1 MT21 MT23 Dak OFF ; triac is initially off
VIka MT1 MT21 ; reverse current sense
* dVdt Turn-on
Emon dvdt0 0 TABLE {ABS(V(MT2,MT1))} (0 0) (2000 2000)
CdVdt dvdt0 dvdt1 100pfd ; displacement current
Rdlay dvdt1 dvdt2 1k
VdVdt dvdt2 MT1 DC 0.0
EdVdt condvdt 0 TABLE {i(vdVdt)-100p*dVdt} (0 0 ) (.1m 10)
RdVdt condvdt 0 1meg
* Gate
Rseries gate gate1 {(Vgt-0.65)/Igt}
Rshunt gate1 gate2 {0.65/Igt}
Dgkf gate1 gate2 Dgk
Dgkr gate2 gate1 Dgk
VIgf gate2 MT1 DC 0.0 ; current sensor
* Gate Turn-on
Egate congate 0 TABLE {(ABS(i(VIgf))-0.95*Igt)} (0 0) (1m 10)
Rgate congate 0 1meg
* Holding current, holding voltage (Quadrant I)
Emain1 main1 0 TABLE {i(VIak)-Ih+5e-3*i(VIgf)/Igt} (0 0) (.1m 1)
Rmain1 main1 0 1meg
Emain2 main2 0 TABLE {v(MT2,MT1)-(Ih*Vtm/Itm)} (0 0) (.1m 1)
Rmain2 main2 0 1meg
Emain3 cnhold 0 TABLE {v(main1,0)*v(main2,0)} (0 0) (1 10)
Rmain3 cnhold 0 1meg
* Holding current, holding voltage (Quadrant III)
Emain1r main1r 0 TABLE {i(VIka)-Ih-5e-3*i(VIgf)/Igt} (0 0) (.1m 1)
Rmain1r main1r 0 1meg
Emain2r main2r 0 TABLE {v(MT1,MT2)-(Ih*Vtm/Itm)} (0 0) (.1m 1)
Rmain2r main2r 0 1meg
Emain3r cnholdr 0 TABLE {v(main1r,0)*v(main2r,0)} (0 0) (1 10)
Rmain3r cnholdr 0 1meg
* Main
Emain4 main4 0 table {(1.0-ABS(i(VIgf))/Igt)} (0 0) (1 1)
Rmain4 main4 0 1meg
Emain5 cnmain 0 table {v(mt2,mt1)-1.05*Vdrm*v(main4)} (0 0) (1 10)
Rmain5 cnmain 0 1meg
Emain5r cnmainr 0 table {v(mt1,mt2)-1.05*Vdrm*v(main4)} (0 0) (1 10)
Rmain5r cnmainr 0 1meg
* Turn-on/Turn-off control (Quadrant I )
Eonoff contot 0 TABLE
+ {v(cnmain)+v(congate)+v(cnhold)+v(condvdt)} (0 0) (10 10)
* Turn-on/Turn-off delays (Quadrant I)
Rton contot dlay1 825
Dton dlay1 cntrol Delay
Rtoff contot dlay2 {2.9E-3/Ton}
Dtoff cntrol dlay2 Delay
Cton cntrol 0 {Ton/454}
* Turn-on/Turn-off control (Quadrant III)
Eonoffr contotr 0 TABLE
+ {v(cnmainr)+v(congate)+v(cnholdr)+v(condvdt)} (0 0) (10 10)
* Turn-on/Turn-off delays (Quadrant III)
Rtonr contotr dlayr1 825
Dtonr dlayr1 cntrolr Delay
Rtoffr contotr dlayr2 {2.9E-3/Ton}
Dtoffr cntrolr dlayr2 Delay
Ctonr cntrolr 0 {Ton/454}
* Controlled switch model
.MODEL Vswitch vswitch
+ (Ron = {(Vtm-0.7)/Itm}, Roff = {1.75E-3*Vdrm/Idrm},
+ Von = 5.0, Voff = 1.5)
* Diodes
.MODEL Dgk D (Is=1E-16 Cjo=50pf Rs=5)
.MODEL Delay D (Is=1E-12 Cjo=5pf Rs=0.01)
.MODEL Dak D (Is=4E-11 Cjo=5pf)
* Allow the gate to float if required
Rfloat gate MT1 1e10
.ends

* R2 subcircuit
.subckt Potentiometer_R2 T1 T2 T3 PARAMS: res=10k posPercent=50
.PARAM relPos = limit(posPercent * 0.01, 0.0000001, 0.9999999)
r1 T1 T2 {{res}*relPos}
r2 T2 T3 {{res} - {res}*relPos}
.ends

* X1 subcircuit
.subckt VIR_LAMP_X1 port1 port2

** resistance of the lamp when conducting current
.param lampResistance = {120^2/40}

** resistance of the lamp after burning out
.param blownResistance = 10e6

** blown signal appears on node blown. 5V = blown, 0 = not
Rdummy blown 0 1000000

** Constant digital high to feed as input to latch
aU2 dU1.DATA d_constsource_U2
.model d_constsource_U2 d_constsource(state=1)

**D-latch to latch state
aU1 dU1.DATA
+ dU1.EN
+ U1_OPEN_SET
+ U1_OPEN_RESET
+ dU1.Q
+ U1_OPEN_notQ D_LATCH

** Output of latch onto node `blown` through DAC
xU1.Q dU1.Q blown TIL_DRV

** Input node `trigger` to latch ENABLE through ADC
xU1.CLK trigger dU1.EN TIL_RCV

** If over blown voltage, trigger DLATCH U1 enable
E2 trigger 0 Value = { if(abs(V(port1, port2)) > 250 & Time > 0, 5, 0) }

** Modelling LIT and HOT states
blit lit 0 v={if(abs(V(port1, port2)) <= 120, {abs(V(port1, port2)) / 120}, 1)}
bhot hot 0 v={abs(V(port1, port2)) >= 120}

** Current sensor
V_Isense port1 lampSense 0

** model of the lamp as a G source so we can change the resistance on the fly
G_Lamp lampSense port2 value = { if( V(blown) < 2.5, V(port1, port2) / lampResistance, V(port1, port2) / blownResistance )}

.subckt TIL_DRV 1 2
* TIL Driver Model 1= D/A input, 2 = out
aDACin1 [1] [2] aDAC
.model aDAC dac_bridge (out_low = 0 out_high = 5 out_undef = 2.5)
.ends

.subckt TIL_RCV 1 2
* TIL Receiver Model 1 = input, 2 = A/D out
aADCin1 [1] [2] ADC
.model ADC adc_bridge (in_low = 2.5 in_high = 2.5)
.ends

.model D_LATCH d_dlatch (data_delay = 1n enable_delay = 1n
+ set_delay = 1n reset_delay = 1n
+ ic = 0 rise_delay = 1n fall_delay = 1n)

.ends
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Dimmer exemplo 5_1 Hart
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