*3 phase full wave controlled rectifier NABIL MUFARRIHAH OCTAVIYANI_181910201104_UNEJ

Waiting for data

Signal	Value
Signal	Value

Cursor 1	Cursor 2	∆X	1/∆X	∆Y	∆Y (Phase)

Out of date
V	—
V	—
V_PP	—
V_RMS	—
V_AV	—
f_V	—
I	—
I	—
I_PP	—
I_RMS	—
I_AV	—
f_I	—
D	—

Out of date
V	—
V	—
V_PP	—
V_RMS	—
V_AV	—
f_V	—
I	—
I	—
I_PP	—
I_RMS	—
I_AV	—
f_I	—
D	—

Out of date
V	—
V	—
V_PP	—
V_RMS	—
V_AV	—
f_V	—
I	—
I	—
I_PP	—
I_RMS	—
I_AV	—
f_I	—
D	—

Out of date
V	—
V	—
V_PP	—
V_RMS	—
V_AV	—
f_V	—
I	—
I	—
I_PP	—
I_RMS	—
I_AV	—
f_I	—
D	—

Out of date
V	—
V	—
V_PP	—
V_RMS	—
V_AV	—
f_V	—
I	—
I	—
I_PP	—
I_RMS	—
I_AV	—
f_I	—
D	—

ID:

x10

x0.1

Sheet:1

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rectifier

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SPICE

SPICE Netlist

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** 3 phase full wave controlled rectifier NABIL MUFARRIHAH OCTAVIYANI_181910201104_UNEJ_ELDA SUJANARKO 2021 **
*
* Multisim Live SPICE netlist
*
*

* --- Circuit Topology ---

* Component: A1
xA1 6 7 ANALOG_DELAY_A1 PARAMS: delay=0

* Component: A2
xA2 6 12 ANALOG_DELAY_A2 PARAMS: delay=0.00333

* Component: A3
xA3 6 8 ANALOG_DELAY_A3 PARAMS: delay=0.00666

* Component: A4
xA4 6 10 ANALOG_DELAY_A4 PARAMS: delay=0.00999

* Component: A5
xA5 6 9 ANALOG_DELAY_A5 PARAMS: delay=0.01332

* Component: A6
xA6 6 11 ANALOG_DELAY_A6 PARAMS: delay=0.01665

* Component: R1
rR1 4 5 1000 VIRTUAL_RESISTANCE_R1

* Component: S1
xS1 1 4 7 SCR_IDEAL_S1 PARAMS: Vth=2.5 Ih=0.01 Vfscr=0 Ron=0.01 Roff=10000000

* Component: S2
xS2 5 3 12 SCR_IDEAL_S2 PARAMS: Vth=2.5 Ih=0.01 Vfscr=0 Ron=0.01 Roff=10000000

* Component: S3
xS3 2 4 8 SCR_IDEAL_S3 PARAMS: Vth=2.5 Ih=0.01 Vfscr=0 Ron=0.01 Roff=10000000

* Component: S4
xS4 5 1 10 SCR_IDEAL_S4 PARAMS: Vth=2.5 Ih=0.01 Vfscr=0 Ron=0.01 Roff=10000000

* Component: S5
xS5 3 4 9 SCR_IDEAL_S5 PARAMS: Vth=2.5 Ih=0.01 Vfscr=0 Ron=0.01 Roff=10000000

* Component: S6
xS6 5 2 11 SCR_IDEAL_S6 PARAMS: Vth=2.5 Ih=0.01 Vfscr=0 Ron=0.01 Roff=10000000

* Component: U1
xU1 1 0 13 6 PHASEANGLE_U1 PARAMS: frequency=50 pulse_width=60 pulse_amplitude=5

* Component: V1
vV1 1 0 dc 0 ac 1 0
+ distof1 0 0
+ distof2 0 0
+ sin ( 0 240 50 0 0 0 )

* Component: V2
vV2 2 0 dc 0 ac 1 0
+ distof1 0 0
+ distof2 0 0
+ sin ( 0 240 50 0 0 -120 )

* Component: V3
vV3 3 0 dc 0 ac 1 0
+ distof1 0 0
+ distof2 0 0
+ sin ( 0 240 50 0 0 120 )

* Component: V4
vV4 13 0 dc 12 ac 5 45
+ distof1 0 0
+ distof2 0 0

* --- Circuit Models ---

* R1 model
.model VIRTUAL_RESISTANCE_R1 r( )

* --- Subcircuits ---

* A1 subcircuit
.subckt ANALOG_DELAY_A1 in out PARAMS: delay=2u
a1 in out adelay
.model adelay analog_delay(delay={delay})
.ends

* A2 subcircuit
.subckt ANALOG_DELAY_A2 in out PARAMS: delay=2u
a1 in out adelay
.model adelay analog_delay(delay={delay})
.ends

* A3 subcircuit
.subckt ANALOG_DELAY_A3 in out PARAMS: delay=2u
a1 in out adelay
.model adelay analog_delay(delay={delay})
.ends

* A4 subcircuit
.subckt ANALOG_DELAY_A4 in out PARAMS: delay=2u
a1 in out adelay
.model adelay analog_delay(delay={delay})
.ends

* A5 subcircuit
.subckt ANALOG_DELAY_A5 in out PARAMS: delay=2u
a1 in out adelay
.model adelay analog_delay(delay={delay})
.ends

* A6 subcircuit
.subckt ANALOG_DELAY_A6 in out PARAMS: delay=2u
a1 in out adelay
.model adelay analog_delay(delay={delay})
.ends

* S1 subcircuit
.subckt SCR_IDEAL_S1 Anode Cathode Gate PARAMS: Vth=2.5 Ih=0 Vfscr=0 Ron=1m Roff=1meg
E3 a2 0 Value = { if(I(vIscr)<=Ih,5,0) }

vIscr Anode 10 dc 0

xU6 8 cathode DIODE_IDEAL params: Vf={Vfscr} Rd={Ron/2} Rdoff={Roff/2}
.subckt DIODE_IDEAL a k params: Vf=0 Rd=1m Rdoff=1meg
ad1 %vd(a k) %id(a k) diode1
.model diode1 pwl(x_array=[{Vf-1} {Vf} {Vf+1}] y_array=[{-1/Rdoff} 0 {1/Rd}] fraction=false input_domain=0.0)
.ends

xS1 10 8 a3 0 VSwitchS1
.subckt VSwitchS1 1 2 3 4
S1 1 2 3 4 vsw0
.model vsw0 vswitch ( Roff={Roff/2} Ron={Ron/2} Voff=0 Von=1 )
.ends

aU5 7 d_constsource_U5
.model d_constsource_U5 d_constsource(state=1)

aU4 [a1 dU4.B dU4.C] reset AND2__TIL__1
xU4.B a2 dU4.B TIL_RCV__NON__1
xU4.C a3 dU4.C TIL_RCV__NON__1
aU3 dU3.A a1 NOT__TIL__1

xU3.A gate dU3.A TIL_RCV__NON__1_Gate

aU2 dU2.S reset 7
+ U2_OPEN_SET U2_OPEN_RESET
+ dU2.Q U2_OPEN_notQ SR_LATCH__TIL__1

xU2.S gate dU2.S TIL_RCV__NON__1_Gate

xU2.Q dU2.Q a3 TIL_DRV__NON__1

.MODEL AND2__TIL__1 d_and ( rise_delay = 1n fall_delay = 1n)
.MODEL NOT__TIL__1 d_inverter (rise_delay = 1n fall_delay = 1n)
.SUBCKT TIL_DRV__NON__1 1 2
* TIL Driver Model 1 = D/A input, 2 = out
aDACin1 [1] [2] aDAC
.MODEL aDAC dac_bridge (out_low= 0 out_high = 5 out_undef = 0)
.ENDS

.SUBCKT TIL_RCV__NON__1_Gate 1 2
* TIL Receiver Model 1 = input, 2 = A/D out
aADCin1 [1] [2] ADC
.MODEL ADC adc_bridge (in_low= {Vth} in_high = {Vth})
.ENDS

.SUBCKT TIL_RCV__NON__1 1 2
* TIL Receiver Model 1 = input, 2 = A/D out
aADCin1 [1] [2] ADC
.MODEL ADC adc_bridge (in_low= 2.5 in_high = 2.5)
.ENDS

.MODEL SR_LATCH__TIL__1 d_srlatch (sr_delay = 1n enable_delay = 1n
+ set_delay = 1n reset_delay= 1n
+ ic = 0 rise_delay = 1n fall_delay = 1n)

.ends

* S2 subcircuit
.subckt SCR_IDEAL_S2 Anode Cathode Gate PARAMS: Vth=2.5 Ih=0 Vfscr=0 Ron=1m Roff=1meg
E3 a2 0 Value = { if(I(vIscr)<=Ih,5,0) }

vIscr Anode 10 dc 0

xU6 8 cathode DIODE_IDEAL params: Vf={Vfscr} Rd={Ron/2} Rdoff={Roff/2}
.subckt DIODE_IDEAL a k params: Vf=0 Rd=1m Rdoff=1meg
ad1 %vd(a k) %id(a k) diode1
.model diode1 pwl(x_array=[{Vf-1} {Vf} {Vf+1}] y_array=[{-1/Rdoff} 0 {1/Rd}] fraction=false input_domain=0.0)
.ends

xS1 10 8 a3 0 VSwitchS1
.subckt VSwitchS1 1 2 3 4
S1 1 2 3 4 vsw0
.model vsw0 vswitch ( Roff={Roff/2} Ron={Ron/2} Voff=0 Von=1 )
.ends

aU5 7 d_constsource_U5
.model d_constsource_U5 d_constsource(state=1)

aU4 [a1 dU4.B dU4.C] reset AND2__TIL__1
xU4.B a2 dU4.B TIL_RCV__NON__1
xU4.C a3 dU4.C TIL_RCV__NON__1
aU3 dU3.A a1 NOT__TIL__1

xU3.A gate dU3.A TIL_RCV__NON__1_Gate

aU2 dU2.S reset 7
+ U2_OPEN_SET U2_OPEN_RESET
+ dU2.Q U2_OPEN_notQ SR_LATCH__TIL__1

xU2.S gate dU2.S TIL_RCV__NON__1_Gate

xU2.Q dU2.Q a3 TIL_DRV__NON__1

.MODEL AND2__TIL__1 d_and ( rise_delay = 1n fall_delay = 1n)
.MODEL NOT__TIL__1 d_inverter (rise_delay = 1n fall_delay = 1n)
.SUBCKT TIL_DRV__NON__1 1 2
* TIL Driver Model 1 = D/A input, 2 = out
aDACin1 [1] [2] aDAC
.MODEL aDAC dac_bridge (out_low= 0 out_high = 5 out_undef = 0)
.ENDS

.SUBCKT TIL_RCV__NON__1_Gate 1 2
* TIL Receiver Model 1 = input, 2 = A/D out
aADCin1 [1] [2] ADC
.MODEL ADC adc_bridge (in_low= {Vth} in_high = {Vth})
.ENDS

.SUBCKT TIL_RCV__NON__1 1 2
* TIL Receiver Model 1 = input, 2 = A/D out
aADCin1 [1] [2] ADC
.MODEL ADC adc_bridge (in_low= 2.5 in_high = 2.5)
.ENDS

.MODEL SR_LATCH__TIL__1 d_srlatch (sr_delay = 1n enable_delay = 1n
+ set_delay = 1n reset_delay= 1n
+ ic = 0 rise_delay = 1n fall_delay = 1n)

.ends

* S3 subcircuit
.subckt SCR_IDEAL_S3 Anode Cathode Gate PARAMS: Vth=2.5 Ih=0 Vfscr=0 Ron=1m Roff=1meg
E3 a2 0 Value = { if(I(vIscr)<=Ih,5,0) }

vIscr Anode 10 dc 0

xU6 8 cathode DIODE_IDEAL params: Vf={Vfscr} Rd={Ron/2} Rdoff={Roff/2}
.subckt DIODE_IDEAL a k params: Vf=0 Rd=1m Rdoff=1meg
ad1 %vd(a k) %id(a k) diode1
.model diode1 pwl(x_array=[{Vf-1} {Vf} {Vf+1}] y_array=[{-1/Rdoff} 0 {1/Rd}] fraction=false input_domain=0.0)
.ends

xS1 10 8 a3 0 VSwitchS1
.subckt VSwitchS1 1 2 3 4
S1 1 2 3 4 vsw0
.model vsw0 vswitch ( Roff={Roff/2} Ron={Ron/2} Voff=0 Von=1 )
.ends

aU5 7 d_constsource_U5
.model d_constsource_U5 d_constsource(state=1)

aU4 [a1 dU4.B dU4.C] reset AND2__TIL__1
xU4.B a2 dU4.B TIL_RCV__NON__1
xU4.C a3 dU4.C TIL_RCV__NON__1
aU3 dU3.A a1 NOT__TIL__1

xU3.A gate dU3.A TIL_RCV__NON__1_Gate

aU2 dU2.S reset 7
+ U2_OPEN_SET U2_OPEN_RESET
+ dU2.Q U2_OPEN_notQ SR_LATCH__TIL__1

xU2.S gate dU2.S TIL_RCV__NON__1_Gate

xU2.Q dU2.Q a3 TIL_DRV__NON__1

.MODEL AND2__TIL__1 d_and ( rise_delay = 1n fall_delay = 1n)
.MODEL NOT__TIL__1 d_inverter (rise_delay = 1n fall_delay = 1n)
.SUBCKT TIL_DRV__NON__1 1 2
* TIL Driver Model 1 = D/A input, 2 = out
aDACin1 [1] [2] aDAC
.MODEL aDAC dac_bridge (out_low= 0 out_high = 5 out_undef = 0)
.ENDS

.SUBCKT TIL_RCV__NON__1_Gate 1 2
* TIL Receiver Model 1 = input, 2 = A/D out
aADCin1 [1] [2] ADC
.MODEL ADC adc_bridge (in_low= {Vth} in_high = {Vth})
.ENDS

.SUBCKT TIL_RCV__NON__1 1 2
* TIL Receiver Model 1 = input, 2 = A/D out
aADCin1 [1] [2] ADC
.MODEL ADC adc_bridge (in_low= 2.5 in_high = 2.5)
.ENDS

.MODEL SR_LATCH__TIL__1 d_srlatch (sr_delay = 1n enable_delay = 1n
+ set_delay = 1n reset_delay= 1n
+ ic = 0 rise_delay = 1n fall_delay = 1n)

.ends

* S4 subcircuit
.subckt SCR_IDEAL_S4 Anode Cathode Gate PARAMS: Vth=2.5 Ih=0 Vfscr=0 Ron=1m Roff=1meg
E3 a2 0 Value = { if(I(vIscr)<=Ih,5,0) }

vIscr Anode 10 dc 0

xU6 8 cathode DIODE_IDEAL params: Vf={Vfscr} Rd={Ron/2} Rdoff={Roff/2}
.subckt DIODE_IDEAL a k params: Vf=0 Rd=1m Rdoff=1meg
ad1 %vd(a k) %id(a k) diode1
.model diode1 pwl(x_array=[{Vf-1} {Vf} {Vf+1}] y_array=[{-1/Rdoff} 0 {1/Rd}] fraction=false input_domain=0.0)
.ends

xS1 10 8 a3 0 VSwitchS1
.subckt VSwitchS1 1 2 3 4
S1 1 2 3 4 vsw0
.model vsw0 vswitch ( Roff={Roff/2} Ron={Ron/2} Voff=0 Von=1 )
.ends

aU5 7 d_constsource_U5
.model d_constsource_U5 d_constsource(state=1)

aU4 [a1 dU4.B dU4.C] reset AND2__TIL__1
xU4.B a2 dU4.B TIL_RCV__NON__1
xU4.C a3 dU4.C TIL_RCV__NON__1
aU3 dU3.A a1 NOT__TIL__1

xU3.A gate dU3.A TIL_RCV__NON__1_Gate

aU2 dU2.S reset 7
+ U2_OPEN_SET U2_OPEN_RESET
+ dU2.Q U2_OPEN_notQ SR_LATCH__TIL__1

xU2.S gate dU2.S TIL_RCV__NON__1_Gate

xU2.Q dU2.Q a3 TIL_DRV__NON__1

.MODEL AND2__TIL__1 d_and ( rise_delay = 1n fall_delay = 1n)
.MODEL NOT__TIL__1 d_inverter (rise_delay = 1n fall_delay = 1n)
.SUBCKT TIL_DRV__NON__1 1 2
* TIL Driver Model 1 = D/A input, 2 = out
aDACin1 [1] [2] aDAC
.MODEL aDAC dac_bridge (out_low= 0 out_high = 5 out_undef = 0)
.ENDS

.SUBCKT TIL_RCV__NON__1_Gate 1 2
* TIL Receiver Model 1 = input, 2 = A/D out
aADCin1 [1] [2] ADC
.MODEL ADC adc_bridge (in_low= {Vth} in_high = {Vth})
.ENDS

.SUBCKT TIL_RCV__NON__1 1 2
* TIL Receiver Model 1 = input, 2 = A/D out
aADCin1 [1] [2] ADC
.MODEL ADC adc_bridge (in_low= 2.5 in_high = 2.5)
.ENDS

.MODEL SR_LATCH__TIL__1 d_srlatch (sr_delay = 1n enable_delay = 1n
+ set_delay = 1n reset_delay= 1n
+ ic = 0 rise_delay = 1n fall_delay = 1n)

.ends

* S5 subcircuit
.subckt SCR_IDEAL_S5 Anode Cathode Gate PARAMS: Vth=2.5 Ih=0 Vfscr=0 Ron=1m Roff=1meg
E3 a2 0 Value = { if(I(vIscr)<=Ih,5,0) }

vIscr Anode 10 dc 0

xU6 8 cathode DIODE_IDEAL params: Vf={Vfscr} Rd={Ron/2} Rdoff={Roff/2}
.subckt DIODE_IDEAL a k params: Vf=0 Rd=1m Rdoff=1meg
ad1 %vd(a k) %id(a k) diode1
.model diode1 pwl(x_array=[{Vf-1} {Vf} {Vf+1}] y_array=[{-1/Rdoff} 0 {1/Rd}] fraction=false input_domain=0.0)
.ends

xS1 10 8 a3 0 VSwitchS1
.subckt VSwitchS1 1 2 3 4
S1 1 2 3 4 vsw0
.model vsw0 vswitch ( Roff={Roff/2} Ron={Ron/2} Voff=0 Von=1 )
.ends

aU5 7 d_constsource_U5
.model d_constsource_U5 d_constsource(state=1)

aU4 [a1 dU4.B dU4.C] reset AND2__TIL__1
xU4.B a2 dU4.B TIL_RCV__NON__1
xU4.C a3 dU4.C TIL_RCV__NON__1
aU3 dU3.A a1 NOT__TIL__1

xU3.A gate dU3.A TIL_RCV__NON__1_Gate

aU2 dU2.S reset 7
+ U2_OPEN_SET U2_OPEN_RESET
+ dU2.Q U2_OPEN_notQ SR_LATCH__TIL__1

xU2.S gate dU2.S TIL_RCV__NON__1_Gate

xU2.Q dU2.Q a3 TIL_DRV__NON__1

.MODEL AND2__TIL__1 d_and ( rise_delay = 1n fall_delay = 1n)
.MODEL NOT__TIL__1 d_inverter (rise_delay = 1n fall_delay = 1n)
.SUBCKT TIL_DRV__NON__1 1 2
* TIL Driver Model 1 = D/A input, 2 = out
aDACin1 [1] [2] aDAC
.MODEL aDAC dac_bridge (out_low= 0 out_high = 5 out_undef = 0)
.ENDS

.SUBCKT TIL_RCV__NON__1_Gate 1 2
* TIL Receiver Model 1 = input, 2 = A/D out
aADCin1 [1] [2] ADC
.MODEL ADC adc_bridge (in_low= {Vth} in_high = {Vth})
.ENDS

.SUBCKT TIL_RCV__NON__1 1 2
* TIL Receiver Model 1 = input, 2 = A/D out
aADCin1 [1] [2] ADC
.MODEL ADC adc_bridge (in_low= 2.5 in_high = 2.5)
.ENDS

.MODEL SR_LATCH__TIL__1 d_srlatch (sr_delay = 1n enable_delay = 1n
+ set_delay = 1n reset_delay= 1n
+ ic = 0 rise_delay = 1n fall_delay = 1n)

.ends

* S6 subcircuit
.subckt SCR_IDEAL_S6 Anode Cathode Gate PARAMS: Vth=2.5 Ih=0 Vfscr=0 Ron=1m Roff=1meg
E3 a2 0 Value = { if(I(vIscr)<=Ih,5,0) }

vIscr Anode 10 dc 0

xU6 8 cathode DIODE_IDEAL params: Vf={Vfscr} Rd={Ron/2} Rdoff={Roff/2}
.subckt DIODE_IDEAL a k params: Vf=0 Rd=1m Rdoff=1meg
ad1 %vd(a k) %id(a k) diode1
.model diode1 pwl(x_array=[{Vf-1} {Vf} {Vf+1}] y_array=[{-1/Rdoff} 0 {1/Rd}] fraction=false input_domain=0.0)
.ends

xS1 10 8 a3 0 VSwitchS1
.subckt VSwitchS1 1 2 3 4
S1 1 2 3 4 vsw0
.model vsw0 vswitch ( Roff={Roff/2} Ron={Ron/2} Voff=0 Von=1 )
.ends

aU5 7 d_constsource_U5
.model d_constsource_U5 d_constsource(state=1)

aU4 [a1 dU4.B dU4.C] reset AND2__TIL__1
xU4.B a2 dU4.B TIL_RCV__NON__1
xU4.C a3 dU4.C TIL_RCV__NON__1
aU3 dU3.A a1 NOT__TIL__1

xU3.A gate dU3.A TIL_RCV__NON__1_Gate

aU2 dU2.S reset 7
+ U2_OPEN_SET U2_OPEN_RESET
+ dU2.Q U2_OPEN_notQ SR_LATCH__TIL__1

xU2.S gate dU2.S TIL_RCV__NON__1_Gate

xU2.Q dU2.Q a3 TIL_DRV__NON__1

.MODEL AND2__TIL__1 d_and ( rise_delay = 1n fall_delay = 1n)
.MODEL NOT__TIL__1 d_inverter (rise_delay = 1n fall_delay = 1n)
.SUBCKT TIL_DRV__NON__1 1 2
* TIL Driver Model 1 = D/A input, 2 = out
aDACin1 [1] [2] aDAC
.MODEL aDAC dac_bridge (out_low= 0 out_high = 5 out_undef = 0)
.ENDS

.SUBCKT TIL_RCV__NON__1_Gate 1 2
* TIL Receiver Model 1 = input, 2 = A/D out
aADCin1 [1] [2] ADC
.MODEL ADC adc_bridge (in_low= {Vth} in_high = {Vth})
.ENDS

.SUBCKT TIL_RCV__NON__1 1 2
* TIL Receiver Model 1 = input, 2 = A/D out
aADCin1 [1] [2] ADC
.MODEL ADC adc_bridge (in_low= 2.5 in_high = 2.5)
.ENDS

.MODEL SR_LATCH__TIL__1 d_srlatch (sr_delay = 1n enable_delay = 1n
+ set_delay = 1n reset_delay= 1n
+ ic = 0 rise_delay = 1n fall_delay = 1n)

.ends

* U1 subcircuit
.subckt PHASEANGLE_U1 sync+ sync- alpha pulse Params: frequency=1 pulse_width=1 pulse_amplitude=1
A1 %vd(sync+,sync-) alpha %vd(pulse,0) alphamod
.model alphamod phase_angle_controller(freq={frequency} pulse_width={pulse_width} pulse_amplitude={pulse_amplitude})
.ends

Errors and Warnings

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Item

Document

Section

Only one section is available for multisection components.

Type

Rise time

Time it takes for signal to transition from low to high.

With non-zero rise time, the signal converts to an analog signal from a digital signal.

Fall time

Time it takes for signal to transition from high to low.

With non-zero fall time, the signal converts to an analog signal from a digital signal.

Use document settings

Use logic levels settings from Document tab.

Threshold voltage levels.

Threshold voltage values used in the logic evaluation. See Digital Simulation for more information.

Output low

Output low voltage.

Maximum output voltage level to produce a low signal.

Input low threshold

Input low threshold voltage.

Maximum input voltage level for the signal to be considered low.

Input high threshold

Input high threshold voltage.

Minimum input voltage level for the signal to be considered high.

Output high

Output high voltage.

Minimum output voltage level to produce a high signal.

Type Probe

Select desired function.

Function

Use document settings

Use logic levels settings from Document tab.

Threshold voltage levels.

Threshold voltage values used in the logic evaluation. See Digital Simulation for more information.

Output low

Output low voltage.

Maximum output voltage level to produce a low signal.

Input low threshold

Input low threshold voltage.

Maximum input voltage level for the signal to be considered low.

Input high threshold

Input high threshold voltage.

Minimum input voltage level for the signal to be considered high.

Output high

Output high voltage.

Minimum output voltage level to produce a high signal.

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Source

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Instantaneous

Displays instantaneous measurements on probe during interactive simulation.

Periodic

Displays periodic measurements on probe during Interactive simulation.

Bias point(s)

Displays bias points on probe for DC Op simulation.

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Name 3 phase full wave controlled rectifier NABIL MUFARRIHAH OCTAVIYANI_181910201104_UNEJ_ELDA SUJANARKO 2021

Type Schematic

The simulation to run. See Simulation types for more information.

Name

Title of graph. Edit as desired.

End time

Time at which the simulation stops. Does not include pauses. Simulation does not occur in real time.

Start simulation

RELTOL

Relative error tolerance. A simulation wide accuracy control used to establish convergence.

VNTOL

Absolute voltage error tolerance. Defines the minimum value for voltage where it may still be considered accurate.

ABSTOL

Absolute current error tolerance. Defines the minimum value for current where it may still be considered accurate.

ITL1

DC iteration limit. Number of iterative passes done on DC circuit equations in attempt to reach convergence in simulation.

ITL4

Upper iteration limit. Number of iterative passes done per time point, on Transient circuit equations in attempt to reach convergence in simulation.

Integration method. The numerical integration method used in transient analysis.

Temp

℃

Operating temperature. The temperature at which the entire circuit will be simulated.

Insert shunt resistance

Inserts a resistance of RSHUNT from every analog node to ground. Will aid in convergence, but alter the behavior of the circuit.

RSHUNT

Shunt resistance. This eliminates singular matrix errors that result from a lack of a DC path to ground.

Reset to default

Threshold voltage levels.

Threshold voltage values used in the logic evaluation. See Digital Simulation for more information.

Output low

Output low voltage.

Maximum output voltage level to produce a low signal.

Input low threshold

Input low threshold voltage.

Maximum input voltage level for the signal to be considered low.

Input high threshold

Input high threshold voltage.

Minimum input voltage level for the signal to be considered high.

Output high

Output high voltage.

Minimum output voltage level to produce a high signal.

Width

Sheet width in grid squares.

Height

Sheet height in grid squares.

Grid

Toggles grid display.

Net Labels

Toggles all net labels.

Component Labels

Toggles all component labels.

3 phase full wave controlled rectifier NABIL MUFARRIHAH OCTAVIYANI_181910201104_UNEJ_ELDA SUJANARKO 2021