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ABCDOAODOEOFOCOBOG~LT~RBI~BI/RBOABCnSUMCn+1ABCnSUMCn+1 5VV1X1X0X1X0V35VY1Y0Y1Y074LS47NU10U115VV2S2S1S0220ΩR1R2220ΩR3220ΩR4220ΩR5220ΩR6220ΩR7220ΩV45V74LS183DU1U274LS183D5 0/1 0/1 0/1 0/1 0/1 0/1 0/1
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ID:

ID:

x10
x0.1
Sheet:1
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74LS183D
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SPICE
SPICE Netlist

This is a text-based representation of the circuit.
The * symbol indicates a comment.
The + symbol indicates a continuation from the previous line.
Probes do not appear in netlists.

** 2.3.5 (2) **
*
* Multisim Live SPICE netlist
*
*

* --- Circuit Topology ---

* Component: R1
rR1 20 25 220 VIRTUAL_RESISTANCE_R1

* Component: R2
rR2 21 26 220 VIRTUAL_RESISTANCE_R2

* Component: R3
rR3 22 31 220 VIRTUAL_RESISTANCE_R3

* Component: R4
rR4 23 30 220 VIRTUAL_RESISTANCE_R4

* Component: R5
rR5 24 29 220 VIRTUAL_RESISTANCE_R5

* Component: R6
rR6 19 28 220 VIRTUAL_RESISTANCE_R6

* Component: R7
rR7 18 27 220 VIRTUAL_RESISTANCE_R7

* Component: U1
xU1 bridgeU1!A bridgeU1!B bridgeU1!Cn 14 5 74LS183D_U1

xbridgeU1!A bridgeU1!A 3 REAL_CUSTOM_ADC PARAMS: lowV=0 maxLowV=0.8 unknownV=1 minHighV=2 highV=3.3 riseT=0 fallT=0

xbridgeU1!B bridgeU1!B 7 REAL_CUSTOM_ADC PARAMS: lowV=0 maxLowV=0.8 unknownV=1 minHighV=2 highV=3.3 riseT=0 fallT=0

xbridgeU1!Cn bridgeU1!Cn 0 REAL_CUSTOM_ADC PARAMS: lowV=0 maxLowV=0.8 unknownV=1 minHighV=2 highV=3.3 riseT=0 fallT=0

* Component: U10
xU10 14 15 16 bridgeU10!D bridgeU10!~LT bridgeU10!~RBI bridgeU10!~BI/RBO bridgeU10!OA bridgeU10!OD bridgeU10!OE bridgeU10!OF bridgeU10!OC bridgeU10!OB bridgeU10!OG 74LS47_U10 PARAMS: Rise_delay=1e-7 Fall_delay=1e-7

xbridgeU10!D bridgeU10!D 0 REAL_CUSTOM_ADC PARAMS: lowV=0 maxLowV=0.8 unknownV=1 minHighV=2 highV=3.3 riseT=0 fallT=0

xbridgeU10!~LT bridgeU10!~LT 17 REAL_CUSTOM_ADC PARAMS: lowV=0 maxLowV=0.8 unknownV=1 minHighV=2 highV=3.3 riseT=0 fallT=0

xbridgeU10!~RBI bridgeU10!~RBI 17 REAL_CUSTOM_ADC PARAMS: lowV=0 maxLowV=0.8 unknownV=1 minHighV=2 highV=3.3 riseT=0 fallT=0

xbridgeU10!~BI/RBO bridgeU10!~BI/RBO 17 REAL_CUSTOM_ADC PARAMS: lowV=0 maxLowV=0.8 unknownV=1 minHighV=2 highV=3.3 riseT=0 fallT=0

xbridgeU10!OA bridgeU10!OA 20 REAL_CUSTOM_DAC PARAMS: lowV=0 maxLowV=0.8 unknownV=1 minHighV=2 highV=3.3 riseT=0 fallT=0

xbridgeU10!OD bridgeU10!OD 23 REAL_CUSTOM_DAC PARAMS: lowV=0 maxLowV=0.8 unknownV=1 minHighV=2 highV=3.3 riseT=0 fallT=0

xbridgeU10!OE bridgeU10!OE 24 REAL_CUSTOM_DAC PARAMS: lowV=0 maxLowV=0.8 unknownV=1 minHighV=2 highV=3.3 riseT=0 fallT=0

xbridgeU10!OF bridgeU10!OF 19 REAL_CUSTOM_DAC PARAMS: lowV=0 maxLowV=0.8 unknownV=1 minHighV=2 highV=3.3 riseT=0 fallT=0

xbridgeU10!OC bridgeU10!OC 22 REAL_CUSTOM_DAC PARAMS: lowV=0 maxLowV=0.8 unknownV=1 minHighV=2 highV=3.3 riseT=0 fallT=0

xbridgeU10!OB bridgeU10!OB 21 REAL_CUSTOM_DAC PARAMS: lowV=0 maxLowV=0.8 unknownV=1 minHighV=2 highV=3.3 riseT=0 fallT=0

xbridgeU10!OG bridgeU10!OG 18 REAL_CUSTOM_DAC PARAMS: lowV=0 maxLowV=0.8 unknownV=1 minHighV=2 highV=3.3 riseT=0 fallT=0

* Component: U11
xU11 25 26 31 30 29 28 27 32 7_SEGMENT_CA_U11

* Component: U2
xU2 bridgeU2!A bridgeU2!B 5 15 16 74LS183D_U2

xbridgeU2!A bridgeU2!A 2 REAL_CUSTOM_ADC PARAMS: lowV=0 maxLowV=0.8 unknownV=1 minHighV=2 highV=3.3 riseT=0 fallT=0

xbridgeU2!B bridgeU2!B 6 REAL_CUSTOM_ADC PARAMS: lowV=0 maxLowV=0.8 unknownV=1 minHighV=2 highV=3.3 riseT=0 fallT=0

* Component: V1
vV1 1 0 dc 5 ac 0 0
+ distof1 0 0
+ distof2 0 0

* Component: V2
vV2 17 0 dc 5 ac 0 0
+ distof1 0 0
+ distof2 0 0

* Component: V3
vV3 4 0 dc 5 ac 0 0
+ distof1 0 0
+ distof2 0 0

* Component: V4
vV4 32 0 dc 5 ac 0 0
+ distof1 0 0
+ distof2 0 0

* Component: X0
xX0 0 3 1 SPDT_Switch_X0 Params: Ron=0.0001 Roff=100000000 State=1

* Component: X1
xX1 0 2 1 SPDT_Switch_X1 Params: Ron=0.0001 Roff=100000000 State=1

* Component: Y0
xY0 0 7 4 SPDT_Switch_Y0 Params: Ron=0.0001 Roff=100000000 State=1

* Component: Y1
xY1 0 6 4 SPDT_Switch_Y1 Params: Ron=0.0001 Roff=100000000 State=0


* --- Circuit Models ---

* R1 model
.model VIRTUAL_RESISTANCE_R1 r( )

* R2 model
.model VIRTUAL_RESISTANCE_R2 r( )

* R3 model
.model VIRTUAL_RESISTANCE_R3 r( )

* R4 model
.model VIRTUAL_RESISTANCE_R4 r( )

* R5 model
.model VIRTUAL_RESISTANCE_R5 r( )

* R6 model
.model VIRTUAL_RESISTANCE_R6 r( )

* R7 model
.model VIRTUAL_RESISTANCE_R7 r( )


* --- Subcircuits ---

* U1 subcircuit
.subckt 74LS183D_U1 A B Cn SUM Cnplus1

ainv1 Cn qinv1 inv
ainv2 B qinv2 inv
ainv3 A qinv3 inv

aand1 [qinv1 qinv2] qand1 and
aand2 [qinv2 qinv3] qand2 and
aand3 [qinv1 qinv3] qand3 and
aand4 [Cn qinv2 A] qand4 and
aand5 [qinv1 B A] qand5 and
aand6 [qinv1 qinv2 qinv3] qand6 and
aand7 [Cn B qinv3] qand7 and

anor1 [qand1 qand2 qand3] Cnplus1 nor
anor2 [qand4 qand5 qand6 qand7] SUM nor

.model inv d_inverter
.model and d_and
.model nor d_nor

.ends

* U10 subcircuit
**********************
*74LS47 DECODER/DRIVER BCD-7 SEGMENT WITH
*OPEN-COLLECTOR OUTPUTS
***
.subckt 74LS47_U10 ina inb inc ind ltb rbib bib/rbob a d e f c b g PARAMS: Rise_delay=100n Fall_delay=100n
*FAMILY TTLin TTLin TTLin TTLin TTLin TTLin TTLin
*TTLout TTLout TTLout TTLout TTLout TTLout TTLout
*pinout N 7 1 2 6 13 10 9 15 11 12 14 3 5 4:VCC=16 GND=8
*pinout J 7 1 2 6 13 10 9 15 11 12 14 3 5 4:VCC=16 GND=8
*pinout D 7 1 2 6 13 10 9 15 11 12 14 3 5 4:VCC=16 GND=8

ainv1 rbib rbi inv

ananda1 [ina ltb] a1 nand
anandb1 [inb ltb] b1 nand
anandc1 [inc ltb] c1 nand
anandd1 [ind ind] d1 nand

ananda2 [a1 bib/rbob] a2 nand
anandb2 [b1 bib/rbob] b2 nand
anandc2 [c1 bib/rbob] c2 nand
anandd2 [d1 bib/rbob] d2 nand

anand6 [ltb rbi d1 c1 b1 a1] nandopenc nand

aopenc1 nandopenc bib/rbob open

aand1a [b2 d2] x1 and
aand2a [a1 c2] x2 and
aand3a [a2 b1 c1 d1] x3 and
aor1 [x1 x2 x3] ai or

aand1b [b2 d2] x4 and
aand2b [a2 b1 c2] x5 and
aand3b [a1 b2 c2] x6 and
aor2 [x4 x5 x6] bi or

aand1c [c2 d2] x7 and
aand2c [a1 b2 c1] x8 and
aor3 [x7 x8] ci or

aand1d [a2 b1 c1] x9 and
aand2d [a1 b1 c2] xa and
aand3d [a2 b2 c2] xb and
aor4 [x9 xa xb] di or

aand1e [b1 c2] xc and
aor5 [xc a2] ei or

aand1f [a2 b2] xd and
aand2f [b2 c1] xe and
aand3f [a2 c1 d1] xf and
aor6 [xd xe xf] fi or

aand1g [a2 b2 c2] xg and
aand2g [b1 c1 d1 ltb] xh and
aor7 [xg xh] gi or

aop1 ai a open
aop2 bi b open
aop3 ci c open
aop4 di d open
aop5 ei e open
aop6 fi f open
aop7 gi g open

.model inv d_inverter
.model nand d_nand
.model and d_and
.model or d_or(rise_delay={Rise_delay} fall_delay={Fall_delay})
.model open d_open_c

.ends

* U11 subcircuit
.subckt 7_SEGMENT_CA_U11 K1 K2 K3 K4 K5 K6 K7 A

dd1 A 0vNode1 ledDiodeModel
Vsense1 0vNode1 K1 DC 0
* Interactive sense node
b1 lit1 0 v = { if (i(Vsense1) < 0, 0, if( i(Vsense1) > 0.02, 1, { i(Vsense1) / 0.02 })) }

dd2 A 0vNode2 ledDiodeModel
Vsense2 0vNode2 K2 DC 0
* Interactive sense node
b2 lit2 0 v = { if (i(Vsense2) < 0, 0, if( i(Vsense2) > 0.02, 1, { i(Vsense2) / 0.02 })) }

dd3 A 0vNode3 ledDiodeModel
Vsense3 0vNode3 K3 DC 0
* Interactive sense node
b3 lit3 0 v = { if (i(Vsense3) < 0, 0, if( i(Vsense3) > 0.02, 1, { i(Vsense3) / 0.02 })) }

dd4 A 0vNode4 ledDiodeModel
Vsense4 0vNode4 K4 DC 0
* Interactive sense node
b4 lit4 0 v = { if (i(Vsense4) < 0, 0, if( i(Vsense4) > 0.02, 1, { i(Vsense4) / 0.02 })) }

dd5 A 0vNode5 ledDiodeModel
Vsense5 0vNode5 K5 DC 0
* Interactive sense node
b5 lit5 0 v = { if (i(Vsense5) < 0, 0, if( i(Vsense5) > 0.02, 1, { i(Vsense5) / 0.02 })) }

dd6 A 0vNode6 ledDiodeModel
Vsense6 0vNode6 K6 DC 0
* Interactive sense node
b6 lit6 0 v = { if (i(Vsense6) < 0, 0, if( i(Vsense6) > 0.02, 1, { i(Vsense6) / 0.02 })) }

dd7 A 0vNode7 ledDiodeModel
Vsense7 0vNode7 K7 DC 0
* Interactive sense node
b7 lit7 0 v = { if (i(Vsense7) < 0, 0, if( i(Vsense7) > 0.02, 1, { i(Vsense7) / 0.02 })) }

.model ledDiodeModel D( IS=1e-14 N=1 RS=0 IBV=1e-10 BV=1e+30 CJO=0 M=0.5 VJ=1 )
.ends

* U2 subcircuit
.subckt 74LS183D_U2 A B Cn SUM Cnplus1

ainv1 Cn qinv1 inv
ainv2 B qinv2 inv
ainv3 A qinv3 inv

aand1 [qinv1 qinv2] qand1 and
aand2 [qinv2 qinv3] qand2 and
aand3 [qinv1 qinv3] qand3 and
aand4 [Cn qinv2 A] qand4 and
aand5 [qinv1 B A] qand5 and
aand6 [qinv1 qinv2 qinv3] qand6 and
aand7 [Cn B qinv3] qand7 and

anor1 [qand1 qand2 qand3] Cnplus1 nor
anor2 [qand4 qand5 qand6 qand7] SUM nor

.model inv d_inverter
.model and d_and
.model nor d_nor

.ends

* X0 subcircuit
.subckt SPDT_Switch_X0 port1 port2 port3 Params: Ron=1e-8 Roff=1e30 State=0
V2 state 0 DC {State}
R1 state 6 10
V1 6 0 DC 0
W0 port2 port1 V1 NC_contact
W1 port2 port3 V1 NO_contact
.MODEL NO_contact ISWITCH (ION=0.05 IOFF=0.025 RON={Ron} ROFF={Roff})
.MODEL NC_contact ISWITCH (ION=0.05 IOFF=0.025 RON={Roff} ROFF={Ron})
.ends

* X1 subcircuit
.subckt SPDT_Switch_X1 port1 port2 port3 Params: Ron=1e-8 Roff=1e30 State=0
V2 state 0 DC {State}
R1 state 6 10
V1 6 0 DC 0
W0 port2 port1 V1 NC_contact
W1 port2 port3 V1 NO_contact
.MODEL NO_contact ISWITCH (ION=0.05 IOFF=0.025 RON={Ron} ROFF={Roff})
.MODEL NC_contact ISWITCH (ION=0.05 IOFF=0.025 RON={Roff} ROFF={Ron})
.ends

* Y0 subcircuit
.subckt SPDT_Switch_Y0 port1 port2 port3 Params: Ron=1e-8 Roff=1e30 State=0
V2 state 0 DC {State}
R1 state 6 10
V1 6 0 DC 0
W0 port2 port1 V1 NC_contact
W1 port2 port3 V1 NO_contact
.MODEL NO_contact ISWITCH (ION=0.05 IOFF=0.025 RON={Ron} ROFF={Roff})
.MODEL NC_contact ISWITCH (ION=0.05 IOFF=0.025 RON={Roff} ROFF={Ron})
.ends

* Y1 subcircuit
.subckt SPDT_Switch_Y1 port1 port2 port3 Params: Ron=1e-8 Roff=1e30 State=0
V2 state 0 DC {State}
R1 state 6 10
V1 6 0 DC 0
W0 port2 port1 V1 NC_contact
W1 port2 port3 V1 NO_contact
.MODEL NO_contact ISWITCH (ION=0.05 IOFF=0.025 RON={Ron} ROFF={Roff})
.MODEL NC_contact ISWITCH (ION=0.05 IOFF=0.025 RON={Roff} ROFF={Ron})
.ends


* --- Pin bridge models

.SUBCKT REAL_CUSTOM_ADC 1 2 PARAMS: lowV=0 maxLowV=0.8 unknownV=1.0 minHighV=2.0 highV=5.0 riseT=0 fallT=0
* Ideal Receiver Model 1 = input, 2 = A/D out
aADCin1 [2] [1] ADC
.MODEL ADC adc_bridge (in_low = {maxLowV} in_high = {minHighV})
.ENDS

.SUBCKT REAL_CUSTOM_DAC 1 2 PARAMS: lowV=0 maxLowV=0.8 unknownV=1.0 minHighV=2.0 highV=5.0 riseT=0 fallT=0
* Ideal Driver Model 1 = A/D out, 2 = input
aDACin1 [1] [2] aDAC
.MODEL aDAC dac_bridge (out_low = {lowV} out_high = {highV} out_undef = {unknownV} t_rise = {max(riseT,1e-9)} t_fall = {max(fallT,1e-9)})
.ENDS
Errors and Warnings

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2.3.5 (2)
Schematic

The simulation to run. See Simulation types for more information.

Name

Title of graph. Edit as desired.

End time

s

Time at which the simulation stops. Does not include pauses. Simulation does not occur in real time.

Start simulation

Mode

Threshold voltage levels.

Threshold voltage values used in the logic evaluation. See Digital Simulation for more information.

Output low

V

Output low voltage.

Maximum output voltage level to produce a low signal.

Input low threshold

V

Input low threshold voltage.

Maximum input voltage level for the signal to be considered low.

Input high threshold

V

Input high threshold voltage.

Minimum input voltage level for the signal to be considered high.

Output high

V

Output high voltage.

Minimum output voltage level to produce a high signal.

Width

Sheet width in grid squares.

Height

Sheet height in grid squares.

Grid

Toggles grid display.

Net Labels

Toggles all net labels.

Component Labels

Toggles all component labels.