Initializing Multisim Live ...

Waiting for awesome
Waiting for data
U1100kΩR1R2100kΩR322kΩ0.1μFC102319VV10PR19VV20450U210kΩR422kΩR5670100kΩR680.1μFC2PR2U3100kΩR709R8100kΩC30.1μFR922kΩ1011PR3 V V V
Out of date
V —
V —
VPP —
VRMS —
VAV —
fV —
I —
I —
IPP —
IRMS —
IAV —
fI —
D —
Out of date
V —
V —
VPP —
VRMS —
VAV —
fV —
I —
I —
IPP —
IRMS —
IAV —
fI —
D —
Out of date
V —
V —
VPP —
VRMS —
VAV —
fV —
I —
I —
IPP —
IRMS —
IAV —
fI —
D —

ID:

ID:
x10
x0.1
Sheet:1
Disable streaming
Details
Netlist
Errors
Circuit Details

View and edit circuit details below.
Visibility
Private
Public

Select Public if you want your design to be viewable by all Multisim Live users.

Name

Name of saved file.

Description

Provides context to the design, and an explanation of the circuit operation. This is useful for highlighting theory or critical aspects of the design.
add a tag

Type a string here. Matching tags appear as you type. Tap a matching tag, or enter a new tag.

SPICE
SPICE Netlist

This is a text-based representation of the circuit.
The * symbol indicates a comment.
The + symbol indicates a continuation from the previous line.
Probes do not appear in netlists.

** Function Generator Group 1 **
*
* Multisim Live SPICE netlist
*
*

* --- Circuit Topology ---

* Component: C1
cC1 1 0 1e-7

* Component: C2
cC2 6 8 1e-7

* Component: C3
cC3 10 11 1e-7

* Component: R1
rR1 1 3 100000 VIRTUAL_RESISTANCE_R1

* Component: R2
rR2 3 2 100000 VIRTUAL_RESISTANCE_R2

* Component: R3
rR3 2 0 22000 VIRTUAL_RESISTANCE_R3

* Component: R4
rR4 7 0 10000 VIRTUAL_RESISTANCE_R4

* Component: R5
rR5 3 6 22000 VIRTUAL_RESISTANCE_R5

* Component: R6
rR6 6 8 100000 VIRTUAL_RESISTANCE_R6

* Component: R7
rR7 9 0 100000 VIRTUAL_RESISTANCE_R7

* Component: R8
rR8 10 11 100000 VIRTUAL_RESISTANCE_R8

* Component: R9
rR9 8 10 22000 VIRTUAL_RESISTANCE_R9

* Component: U1
xU1 2 1 4 5 3 5T_VIRTUAL_U1 PARAMS: VOS=0.001 IBS=8e-8 IOS=2e-8 AVOL=200000 BW=100000000 SR=1000000 CMRR=100 ISC=0.025 RI=10000000 RO=10

* Component: U2
xU2 7 6 8 3T_VIRTUAL_U2 PARAMS: VOS=0 IBS=0 IOS=0 AVOL=200000 BW=100000000 RI=10000000 RO=10 VOMP=12 VOMN=-12

* Component: U3
xU3 9 10 11 3T_VIRTUAL_U3 PARAMS: VOS=0 IBS=0 IOS=0 AVOL=200000 BW=100000000 RI=10000000 RO=10 VOMP=12 VOMN=-12

* Component: V1
vV1 4 0 dc 9 ac 0 0
+ distof1 0 0
+ distof2 0 0

* Component: V2
vV2 0 5 dc 9 ac 0 0
+ distof1 0 0
+ distof2 0 0


* --- Circuit Models ---

* R1 model
.model VIRTUAL_RESISTANCE_R1 r( )

* R2 model
.model VIRTUAL_RESISTANCE_R2 r( )

* R3 model
.model VIRTUAL_RESISTANCE_R3 r( )

* R4 model
.model VIRTUAL_RESISTANCE_R4 r( )

* R5 model
.model VIRTUAL_RESISTANCE_R5 r( )

* R6 model
.model VIRTUAL_RESISTANCE_R6 r( )

* R7 model
.model VIRTUAL_RESISTANCE_R7 r( )

* R8 model
.model VIRTUAL_RESISTANCE_R8 r( )

* R9 model
.model VIRTUAL_RESISTANCE_R9 r( )


* --- Subcircuits ---

* U1 subcircuit
.subckt 5T_VIRTUAL_U1 In_p In_n Vpos Vneg Out params: AVOL=200k BW=20Meg CMRR=100
+SR=1Meg RO=75 ISC=25m RI=100meg VOS=0.1m IBS=1n IOS=1p
.param Rp1=1e6
.param Rs1=1e6
.param K_Is2a=sqrt(AVOL)/Rs1
.param K_Is2b=sqrt(AVOL)/Rp1
.param Cp1={AVOL/(2*pi*BW*Rp1)}
.param CMRR_lin=10**(CMRR/20)


Rin In_p In_n {RI}
Bcm 4 3 V = { V(cm)/CMRR_lin}
Voff In_p 4 {VOS}
Ibias1 In_p 0 {IBS}
Ibias2 In_n 0 {IBS}
Ioffset In_p In_n {IOS/2}

Rcm1 In_p cm 10meg
Rcm2 In_n cm 10meg

BIs1a vref vs2a I = { K_Is2a*(V(3)-V(In_n)) }
Rs1 vs2a vref {Rs1}

BIs2b vref vs2b I = { K_Is2b*(V(vs2a)-v(vref)) }
Rp1 vs2b vref {Rp1}
VCp1sense vs2b vs2b_ 0
Cp1 vs2b_ vref {Cp1}


D3 vs2b_ 8 Limit_Diode
D4 8 vpos Limit_Diode
B_SRp 8 vpos I={I(VCp1sense)- (Cp1*SR)}

D5 10 vs2b_ Limit_Diode
D6 Vneg 10 Limit_Diode
B_SRn Vneg 10 I={-1*I(VCp1sense)-(Cp1*SR)}

DVpclip vs2b_ Vpos V_limit
DVnclip Vneg vs2b_ V_limit

Bout vref out_ I={(V(vs2b)-v(vref))/RO}
Rout vref out_ {RO}
Voutsense out_ out 0

D9 out 15 Limit_Diode
D10 15 vpos Limit_Diode
B_outp 15 vpos I={I(Voutsense)- ISC}

D11 16 out Limit_Diode
D12 vneg 16 Limit_Diode
B_outn vneg 16 I={-1*I(Voutsense)-ISC}

R5 Vpos mid 1000000
R6 mid Vneg 1000000
Eref vref 0 mid 0 1

.MODEL Limit_Diode D (IS= 1.0e-12)
.MODEL V_limit D(n=0.1)
.ends

* U2 subcircuit
.SUBCKT 3T_VIRTUAL_U2 in_pos in_neg out PARAMS: AVOL=500k BW=10Meg RI=10Meg RO=0 VOS=0 IBS=0 IOS=0 VOMP=15 VOMN=-15

* Input Stage: Rin, Ibias, Voffset
VOS in_pos 4 {VOS}
Ibias1 4 0 {IBS}
Ibias2 in_neg 0 {IBS}
Ios 4 in_neg {IOS/2}
Rin 4 in_neg {RI}

*Middle stage: Gain, frequency, voltage limiting
Bgain 0 6 I={v(4,in_neg)*AVOL/1meg }
R1 6 0 1meg
CP1 6 0 {AVOL/(2*pi*1meg*BW)}


Vpos 9 0 {VOMP}
Dlimit_pos 6 9 d1

Vneg 10 0 {VOMN}
Dlimit_neg 10 6 d1

.model d1 d(n=0.1)

*Output stage: Buffer, output resistance
E2 7 0 6 0 1
Rout 7 out {RO}
.ends

* U3 subcircuit
.SUBCKT 3T_VIRTUAL_U3 in_pos in_neg out PARAMS: AVOL=500k BW=10Meg RI=10Meg RO=0 VOS=0 IBS=0 IOS=0 VOMP=15 VOMN=-15

* Input Stage: Rin, Ibias, Voffset
VOS in_pos 4 {VOS}
Ibias1 4 0 {IBS}
Ibias2 in_neg 0 {IBS}
Ios 4 in_neg {IOS/2}
Rin 4 in_neg {RI}

*Middle stage: Gain, frequency, voltage limiting
Bgain 0 6 I={v(4,in_neg)*AVOL/1meg }
R1 6 0 1meg
CP1 6 0 {AVOL/(2*pi*1meg*BW)}


Vpos 9 0 {VOMP}
Dlimit_pos 6 9 d1

Vneg 10 0 {VOMN}
Dlimit_neg 10 6 d1

.model d1 d(n=0.1)

*Output stage: Buffer, output resistance
E2 7 0 6 0 1
Rout 7 out {RO}
.ends
Errors and Warnings

Any error, warning or information messages appear below.
Item
Document

Checkboxes toggle displayed values on and off.
Function Generator Group 1
Schematic

The simulation to run. See Simulation types for more information.

Name

Title of graph. Edit as desired.

End time

s

Time at which the simulation stops. Does not include pauses. Simulation does not occur in real time.
Start simulation

Mode
Threshold voltage levels.

Threshold voltage values used in the logic evaluation. See Digital Simulation for more information.

Output low

V
Output low voltage.

Maximum output voltage level to produce a low signal.

Input low threshold

V
Input low threshold voltage.

Maximum input voltage level for the signal to be considered low.

Input high threshold

V
Input high threshold voltage.

Minimum input voltage level for the signal to be considered high.

Output high

V
Output high voltage.

Minimum output voltage level to produce a high signal.

Width

Sheet width in grid squares.

Height

Sheet height in grid squares.

Grid

Toggles grid display.

Net Labels

Toggles all net labels.

Component Labels

Toggles all component labels.