*3.2.4 Asynchronous Counters Now Serving Display

Waiting for data

Signal	Value
Signal	Value

Cursor 1	Cursor 2	∆X	1/∆X	∆Y	∆Y (Phase)

ID:

x10

x0.1

Sheet:1

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SPICE

SPICE Netlist

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** 3.2.4 Asynchronous Counters Now Serving Display **
*
* Multisim Live SPICE netlist
*
*

* --- Circuit Topology ---

* Component: DG1
aDG1 bridgeDG1!OUT Digital_Source_DG1

xbridgeDG1!OUT bridgeDG1!OUT 39 REAL_CUSTOM_DAC PARAMS: lowV=0 maxLowV=0.8 unknownV=1 minHighV=2 highV=3.3 riseT=0 fallT=0

* Component: DG2
aDG2 bridgeDG2!OUT Digital_Source_DG2

xbridgeDG2!OUT bridgeDG2!OUT 40 REAL_CUSTOM_DAC PARAMS: lowV=0 maxLowV=0.8 unknownV=1 minHighV=2 highV=3.3 riseT=0 fallT=0

* Component: DG3
aDG3 bridgeDG3!OUT Digital_Source_DG3

xbridgeDG3!OUT bridgeDG3!OUT 24 REAL_CUSTOM_DAC PARAMS: lowV=0 maxLowV=0.8 unknownV=1 minHighV=2 highV=3.3 riseT=0 fallT=0

* Component: DG4
aDG4 37 Digital_Source_DG4

* Component: DG5
aDG5 36 Digital_Source_DG5

* Component: DG8
aDG8 16 Digital_Source_DG8

* Component: DG9
aDG9 18 Digital_Source_DG9

* Component: S1
xS1 40 23 39 SPDT_Switch_S1 Params: Ron=0.0001 Roff=100000000 State=1

* Component: U1
aU1 [15 13] 19 Digital_AND2_U1

* Component: U10
xU10 1 2 3 4 9 10 11 24 7_SEGMENT_CC_U10

* Component: U13
xU13 32 33 34 35 37 37 37 bridgeU13!OA bridgeU13!OD bridgeU13!OE bridgeU13!OF bridgeU13!OC bridgeU13!OB bridgeU13!OG 74LS48_U13 PARAMS: Rise_delay=1e-7 Fall_delay=1e-7

xbridgeU13!OA bridgeU13!OA 25 REAL_CUSTOM_DAC PARAMS: lowV=0 maxLowV=0.8 unknownV=1 minHighV=2 highV=3.3 riseT=0 fallT=0

xbridgeU13!OD bridgeU13!OD 28 REAL_CUSTOM_DAC PARAMS: lowV=0 maxLowV=0.8 unknownV=1 minHighV=2 highV=3.3 riseT=0 fallT=0

xbridgeU13!OE bridgeU13!OE 29 REAL_CUSTOM_DAC PARAMS: lowV=0 maxLowV=0.8 unknownV=1 minHighV=2 highV=3.3 riseT=0 fallT=0

xbridgeU13!OF bridgeU13!OF 30 REAL_CUSTOM_DAC PARAMS: lowV=0 maxLowV=0.8 unknownV=1 minHighV=2 highV=3.3 riseT=0 fallT=0

xbridgeU13!OC bridgeU13!OC 27 REAL_CUSTOM_DAC PARAMS: lowV=0 maxLowV=0.8 unknownV=1 minHighV=2 highV=3.3 riseT=0 fallT=0

xbridgeU13!OB bridgeU13!OB 26 REAL_CUSTOM_DAC PARAMS: lowV=0 maxLowV=0.8 unknownV=1 minHighV=2 highV=3.3 riseT=0 fallT=0

xbridgeU13!OG bridgeU13!OG 31 REAL_CUSTOM_DAC PARAMS: lowV=0 maxLowV=0.8 unknownV=1 minHighV=2 highV=3.3 riseT=0 fallT=0

* Component: U14
aU14 [35 7 6 32] 38 Digital_NAND4_U14

* Component: U2
aU2 [15 13] 20 Digital_AND2_U2

* Component: U20
xU20 17 12 19 18 15 14 13 12 74LS93_U20

* Component: U21
xU21 12 13 14 15 16 16 16 bridgeU21!OA bridgeU21!OD bridgeU21!OE bridgeU21!OF bridgeU21!OC bridgeU21!OB bridgeU21!OG 74LS48_U21 PARAMS: Rise_delay=1e-7 Fall_delay=1e-7

xbridgeU21!OA bridgeU21!OA 1 REAL_CUSTOM_DAC PARAMS: lowV=0 maxLowV=0.8 unknownV=1 minHighV=2 highV=3.3 riseT=0 fallT=0

xbridgeU21!OD bridgeU21!OD 4 REAL_CUSTOM_DAC PARAMS: lowV=0 maxLowV=0.8 unknownV=1 minHighV=2 highV=3.3 riseT=0 fallT=0

xbridgeU21!OE bridgeU21!OE 9 REAL_CUSTOM_DAC PARAMS: lowV=0 maxLowV=0.8 unknownV=1 minHighV=2 highV=3.3 riseT=0 fallT=0

xbridgeU21!OF bridgeU21!OF 10 REAL_CUSTOM_DAC PARAMS: lowV=0 maxLowV=0.8 unknownV=1 minHighV=2 highV=3.3 riseT=0 fallT=0

xbridgeU21!OC bridgeU21!OC 3 REAL_CUSTOM_DAC PARAMS: lowV=0 maxLowV=0.8 unknownV=1 minHighV=2 highV=3.3 riseT=0 fallT=0

xbridgeU21!OB bridgeU21!OB 2 REAL_CUSTOM_DAC PARAMS: lowV=0 maxLowV=0.8 unknownV=1 minHighV=2 highV=3.3 riseT=0 fallT=0

xbridgeU21!OG bridgeU21!OG 11 REAL_CUSTOM_DAC PARAMS: lowV=0 maxLowV=0.8 unknownV=1 minHighV=2 highV=3.3 riseT=0 fallT=0

* Component: U3
aU3 [bridgeU3!A 22] 17 Digital_AND2_U3

xbridgeU3!A bridgeU3!A 21 REAL_CUSTOM_ADC PARAMS: lowV=0 maxLowV=0.8 unknownV=1 minHighV=2 highV=3.3 riseT=0 fallT=0

* Component: U4
aU4 35 22 Digital_Inverter_U4

* Component: U5
xU5 5 20 36 38 32 5 Digital_DFlipFlop_U5 PARAMS: Negative_Edge_Clock=0 Negative_SET_RESET=1 Rise_delay=1e-9 Fall_delay=1e-9 Clk_delay=1e-9 Set_delay=1e-9 Reset_delay=1e-9 Ic=0

* Component: U6
xU6 6 5 36 38 33 6 Digital_DFlipFlop_U6 PARAMS: Negative_Edge_Clock=0 Negative_SET_RESET=1 Rise_delay=1e-9 Fall_delay=1e-9 Clk_delay=1e-9 Set_delay=1e-9 Reset_delay=1e-9 Ic=0

* Component: U7
xU7 7 6 36 38 34 7 Digital_DFlipFlop_U7 PARAMS: Negative_Edge_Clock=0 Negative_SET_RESET=1 Rise_delay=1e-9 Fall_delay=1e-9 Clk_delay=1e-9 Set_delay=1e-9 Reset_delay=1e-9 Ic=0

* Component: U8
xU8 8 7 38 bridgeU8!RESET 35 8 Digital_DFlipFlop_U8 PARAMS: Negative_Edge_Clock=0 Negative_SET_RESET=1 Rise_delay=1e-9 Fall_delay=1e-9 Clk_delay=1e-9 Set_delay=1e-9 Reset_delay=1e-9 Ic=0

xbridgeU8!RESET bridgeU8!RESET 23 REAL_CUSTOM_ADC PARAMS: lowV=0 maxLowV=0.8 unknownV=1 minHighV=2 highV=3.3 riseT=0 fallT=0

* Component: U9
xU9 25 26 27 28 29 30 31 24 7_SEGMENT_CC_U9

* Component: V3
vV3 21 0
+ pulse( 0 5 0 1e-9 1e-9
+ { 50 * 0.01 / 1000 }
+ { 1/1000 } )

* --- Circuit Models ---

* DG1 model
.model Digital_Source_DG1 d_constsource(State=1)

* DG2 model
.model Digital_Source_DG2 d_constsource(State=0)

* DG3 model
.model Digital_Source_DG3 d_constsource(State=0)

* DG4 model
.model Digital_Source_DG4 d_constsource(State=1)

* DG5 model
.model Digital_Source_DG5 d_constsource(State=1)

* DG8 model
.model Digital_Source_DG8 d_constsource(State=1)

* DG9 model
.model Digital_Source_DG9 d_constsource(State=1)

* U1 model
.model Digital_AND2_U1 d_and (rise_delay=1e-9 fall_delay=1e-9)

* U14 model
.model Digital_NAND4_U14 d_nand (rise_delay=1e-9 fall_delay=1e-9)

* U2 model
.model Digital_AND2_U2 d_and (rise_delay=1e-9 fall_delay=1e-9)

* U3 model
.model Digital_AND2_U3 d_and (rise_delay=1e-9 fall_delay=1e-9)

* U4 model
.model Digital_Inverter_U4 d_inverter (rise_delay=1e-9 fall_delay=1e-9)

* --- Subcircuits ---

* S1 subcircuit
.subckt SPDT_Switch_S1 port1 port2 port3 Params: Ron=1e-8 Roff=1e30 State=0
V2 state 0 DC {State}
R1 state 6 10
V1 6 0 DC 0
W0 port2 port1 V1 NC_contact
W1 port2 port3 V1 NO_contact
.MODEL NO_contact ISWITCH (ION=0.05 IOFF=0.025 RON={Ron} ROFF={Roff})
.MODEL NC_contact ISWITCH (ION=0.05 IOFF=0.025 RON={Roff} ROFF={Ron})
.ends

* U10 subcircuit
.subckt 7_SEGMENT_CC_U10 A1 A2 A3 A4 A5 A6 A7 K

dd1 A1 0vNode1 ledDiodeModel
Vsense1 0vNode1 K DC 0
* Interactive sense node
b1 lit1 0 v = { if (i(Vsense1) < 0, 0, if( i(Vsense1) > 0.02, 1, { i(Vsense1) / 0.02 })) }

dd2 A2 0vNode2 ledDiodeModel
Vsense2 0vNode2 K DC 0
* Interactive sense node
b2 lit2 0 v = { if (i(Vsense2) < 0, 0, if( i(Vsense2) > 0.02, 1, { i(Vsense2) / 0.02 })) }

dd3 A3 0vNode3 ledDiodeModel
Vsense3 0vNode3 K DC 0
* Interactive sense node
b3 lit3 0 v = { if (i(Vsense3) < 0, 0, if( i(Vsense3) > 0.02, 1, { i(Vsense3) / 0.02 })) }

dd4 A4 0vNode4 ledDiodeModel
Vsense4 0vNode4 K DC 0
* Interactive sense node
b4 lit4 0 v = { if (i(Vsense4) < 0, 0, if( i(Vsense4) > 0.02, 1, { i(Vsense4) / 0.02 })) }

dd5 A5 0vNode5 ledDiodeModel
Vsense5 0vNode5 K DC 0
* Interactive sense node
b5 lit5 0 v = { if (i(Vsense5) < 0, 0, if( i(Vsense5) > 0.02, 1, { i(Vsense5) / 0.02 })) }

dd6 A6 0vNode6 ledDiodeModel
Vsense6 0vNode6 K DC 0
* Interactive sense node
b6 lit6 0 v = { if (i(Vsense6) < 0, 0, if( i(Vsense6) > 0.02, 1, { i(Vsense6) / 0.02 })) }

dd7 A7 0vNode7 ledDiodeModel
Vsense7 0vNode7 K DC 0
* Interactive sense node
b7 lit7 0 v = { if (i(Vsense7) < 0, 0, if( i(Vsense7) > 0.02, 1, { i(Vsense7) / 0.02 })) }

.model ledDiodeModel D( IS=1e-14 N=1 RS=0 IBV=1e-10 BV=1e+30 CJO=0 M=0.5 VJ=1 )
.ends

* U13 subcircuit
**********************
*74LS48 DECODER/DRIVER BCD-7 SEGMENT WITH
*2k PULL-UPS OUTPUTS
***
.subckt 74LS48_U13 ina inb inc ind ltb rbib bib/rbob a d e f c b g PARAMS: Rise_delay=100n Fall_delay=100n
*FAMILY TTLin TTLin TTLin TTLin TTLin TTLin TTLin
*TTLout TTLout TTLout TTLout TTLout TTLout TTLout
*pinout N 7 1 2 6 13 10 9 15 11 12 14 3 5 4:VCC=16 GND=8
*pinout J 7 1 2 6 13 10 9 15 11 12 14 3 5 4:VCC=16 GND=8
*pinout D 7 1 2 6 13 10 9 15 11 12 14 3 5 4:VCC=16 GND=8

ainv1 rbib rbi inv

ananda1 [ina ltb] a1 nand
anandb1 [inb ltb] b1 nand
anandc1 [inc ltb] c1 nand
anandd1 [ind ind] d1 nand

ananda2 [a1 bib/rbob] a2 nand
anandb2 [b1 bib/rbob] b2 nand
anandc2 [c1 bib/rbob] c2 nand
anandd2 [d1 bib/rbob] d2 nand

anand6 [ltb rbi d1 c1 b1 a1] nandopenc nand

aopenc1 nandopenc bib/rbob open_c

aand1a [b2 d2] x1 and
aand2a [a1 c2] x2 and
aand3a [a2 b1 c1 d1] x3 and
aor1 [x1 x2 x3] ai or

aand1b [b2 d2] x4 and
aand2b [a2 b1 c2] x5 and
aand3b [a1 b2 c2] x6 and
aor2 [x4 x5 x6] bi or

aand1c [c2 d2] x7 and
aand2c [a1 b2 c1] x8 and
aor3 [x7 x8] ci or

aand1d [a2 b1 c1] x9 and
aand2d [a1 b1 c2] xa and
aand3d [a2 b2 c2] xb and
aor4 [x9 xa xb] di or

aand1e [b1 c2] xc and
aor5 [xc a2] ei or

aand1f [a2 b2] xd and
aand2f [b2 c1] xe and
aand3f [a2 c1 d1] xf and
aor6 [xd xe xf] fi or

aand1g [a2 b2 c2] xg and
aand2g [b1 c1 d1 ltb] xh and
aor7 [xg xh] gi or

ah h high

aand1 [ai h] a nand
aand2 [bi h] b nand
aand3 [ci h] c nand
aand4 [di h] d nand
aand5 [ei h] e nand
aand6 [fi h] f nand
aand7 [gi h] g nand

.model inv d_inverter
.model nand d_nand
.model or d_or(rise_delay={Rise_delay} fall_delay={Fall_delay})
.model and d_and
.model open_c d_open_c
.model high d_pullup(load=2k)

.ends

* U20 subcircuit
**********************
*74LS93 COUNTER BINARY 4-BIT, ASYNCHRONOUS
***
.subckt 74LS93_U20 clka clkb r02 r01 qd qc qb qa
*FAMILY TTLin TTLin TTLin TTLin TTLout
*pinout N 14 1 3 2 11 8 9 12 5:VCC=5 GND=10
*pinout J 11 14 1 3 2 11 8 9 12 5:VCC=5 GND=10
*pinout D 11 14 1 3 2 11 8 9 12 5:VCC=5 GND=10

aand [r01 r02] rst and
ainv1 clka nclka inv
ainv2 clkb nclkb inv

ah high high
al low low

ajkffaqa high high nclka low rst qa nqa jkffaqa
ajkffbqb high high nclkb low rst qb nqb jkffbqb
ajkffbqc high high nqb low rst qc nqc jkffbqc
ajkffbqd high high nqc low rst qd nqd jkffbqd

.model jkffaqa d_jkff
.model jkffbqb d_jkff
.model jkffbqc d_jkff
.model jkffbqd d_jkff
.model inv d_inverter (rise_delay=10p fall_delay=10p)
.model low d_pulldown
.model high d_pullup
.model and d_and

.ends

* U21 subcircuit
**********************
*74LS48 DECODER/DRIVER BCD-7 SEGMENT WITH
*2k PULL-UPS OUTPUTS
***
.subckt 74LS48_U21 ina inb inc ind ltb rbib bib/rbob a d e f c b g PARAMS: Rise_delay=100n Fall_delay=100n
*FAMILY TTLin TTLin TTLin TTLin TTLin TTLin TTLin
*TTLout TTLout TTLout TTLout TTLout TTLout TTLout
*pinout N 7 1 2 6 13 10 9 15 11 12 14 3 5 4:VCC=16 GND=8
*pinout J 7 1 2 6 13 10 9 15 11 12 14 3 5 4:VCC=16 GND=8
*pinout D 7 1 2 6 13 10 9 15 11 12 14 3 5 4:VCC=16 GND=8

ainv1 rbib rbi inv

ananda1 [ina ltb] a1 nand
anandb1 [inb ltb] b1 nand
anandc1 [inc ltb] c1 nand
anandd1 [ind ind] d1 nand

ananda2 [a1 bib/rbob] a2 nand
anandb2 [b1 bib/rbob] b2 nand
anandc2 [c1 bib/rbob] c2 nand
anandd2 [d1 bib/rbob] d2 nand

anand6 [ltb rbi d1 c1 b1 a1] nandopenc nand

aopenc1 nandopenc bib/rbob open_c

aand1a [b2 d2] x1 and
aand2a [a1 c2] x2 and
aand3a [a2 b1 c1 d1] x3 and
aor1 [x1 x2 x3] ai or

aand1b [b2 d2] x4 and
aand2b [a2 b1 c2] x5 and
aand3b [a1 b2 c2] x6 and
aor2 [x4 x5 x6] bi or

aand1c [c2 d2] x7 and
aand2c [a1 b2 c1] x8 and
aor3 [x7 x8] ci or

aand1d [a2 b1 c1] x9 and
aand2d [a1 b1 c2] xa and
aand3d [a2 b2 c2] xb and
aor4 [x9 xa xb] di or

aand1e [b1 c2] xc and
aor5 [xc a2] ei or

aand1f [a2 b2] xd and
aand2f [b2 c1] xe and
aand3f [a2 c1 d1] xf and
aor6 [xd xe xf] fi or

aand1g [a2 b2 c2] xg and
aand2g [b1 c1 d1 ltb] xh and
aor7 [xg xh] gi or

ah h high

aand1 [ai h] a nand
aand2 [bi h] b nand
aand3 [ci h] c nand
aand4 [di h] d nand
aand5 [ei h] e nand
aand6 [fi h] f nand
aand7 [gi h] g nand

.model inv d_inverter
.model nand d_nand
.model or d_or(rise_delay={Rise_delay} fall_delay={Fall_delay})
.model and d_and
.model open_c d_open_c
.model high d_pullup(load=2k)

.ends

* U5 subcircuit
.subckt Digital_DFlipFlop_U5 1 2 3 4 5 6 PARAMS: Negative_Edge_Clock=0 Negative_SET_RESET=0 Clk_delay=1n Set_delay=1n Reset_delay=1n Ic=0 Rise_delay=1n Fall_delay=1n
*PIN MAPPING: D Q ~Q RESET CLK SET
* 1 5 6 4 2 3
*MODELS USED
aDG1 neg_SR Digital_SourceSR
aDG2 neg_clk Digital_SourceCLK
Axor1 [3 neg_SR] set xor
Axor2 [2 neg_clk] clk xor
Axor3 [4 neg_SR] reset xor
Ajkff 1 clk set reset 5 6 D_FF

.model Digital_SourceCLK d_constsource(State={Negative_Edge_Clock})
.model Digital_SourceSR d_constsource(State={Negative_SET_RESET})
.model xor d_xor
.MODEL D_FF d_dff (clk_delay={Clk_delay} set_delay={Set_delay} reset_delay={Reset_delay} ic={Ic} rise_delay={Rise_delay} fall_delay={Fall_delay})
.ENDS

* U6 subcircuit
.subckt Digital_DFlipFlop_U6 1 2 3 4 5 6 PARAMS: Negative_Edge_Clock=0 Negative_SET_RESET=0 Clk_delay=1n Set_delay=1n Reset_delay=1n Ic=0 Rise_delay=1n Fall_delay=1n
*PIN MAPPING: D Q ~Q RESET CLK SET
* 1 5 6 4 2 3
*MODELS USED
aDG1 neg_SR Digital_SourceSR
aDG2 neg_clk Digital_SourceCLK
Axor1 [3 neg_SR] set xor
Axor2 [2 neg_clk] clk xor
Axor3 [4 neg_SR] reset xor
Ajkff 1 clk set reset 5 6 D_FF

.model Digital_SourceCLK d_constsource(State={Negative_Edge_Clock})
.model Digital_SourceSR d_constsource(State={Negative_SET_RESET})
.model xor d_xor
.MODEL D_FF d_dff (clk_delay={Clk_delay} set_delay={Set_delay} reset_delay={Reset_delay} ic={Ic} rise_delay={Rise_delay} fall_delay={Fall_delay})
.ENDS

* U7 subcircuit
.subckt Digital_DFlipFlop_U7 1 2 3 4 5 6 PARAMS: Negative_Edge_Clock=0 Negative_SET_RESET=0 Clk_delay=1n Set_delay=1n Reset_delay=1n Ic=0 Rise_delay=1n Fall_delay=1n
*PIN MAPPING: D Q ~Q RESET CLK SET
* 1 5 6 4 2 3
*MODELS USED
aDG1 neg_SR Digital_SourceSR
aDG2 neg_clk Digital_SourceCLK
Axor1 [3 neg_SR] set xor
Axor2 [2 neg_clk] clk xor
Axor3 [4 neg_SR] reset xor
Ajkff 1 clk set reset 5 6 D_FF

.model Digital_SourceCLK d_constsource(State={Negative_Edge_Clock})
.model Digital_SourceSR d_constsource(State={Negative_SET_RESET})
.model xor d_xor
.MODEL D_FF d_dff (clk_delay={Clk_delay} set_delay={Set_delay} reset_delay={Reset_delay} ic={Ic} rise_delay={Rise_delay} fall_delay={Fall_delay})
.ENDS

* U8 subcircuit
.subckt Digital_DFlipFlop_U8 1 2 3 4 5 6 PARAMS: Negative_Edge_Clock=0 Negative_SET_RESET=0 Clk_delay=1n Set_delay=1n Reset_delay=1n Ic=0 Rise_delay=1n Fall_delay=1n
*PIN MAPPING: D Q ~Q RESET CLK SET
* 1 5 6 4 2 3
*MODELS USED
aDG1 neg_SR Digital_SourceSR
aDG2 neg_clk Digital_SourceCLK
Axor1 [3 neg_SR] set xor
Axor2 [2 neg_clk] clk xor
Axor3 [4 neg_SR] reset xor
Ajkff 1 clk set reset 5 6 D_FF

.model Digital_SourceCLK d_constsource(State={Negative_Edge_Clock})
.model Digital_SourceSR d_constsource(State={Negative_SET_RESET})
.model xor d_xor
.MODEL D_FF d_dff (clk_delay={Clk_delay} set_delay={Set_delay} reset_delay={Reset_delay} ic={Ic} rise_delay={Rise_delay} fall_delay={Fall_delay})
.ENDS

* U9 subcircuit
.subckt 7_SEGMENT_CC_U9 A1 A2 A3 A4 A5 A6 A7 K

dd1 A1 0vNode1 ledDiodeModel
Vsense1 0vNode1 K DC 0
* Interactive sense node
b1 lit1 0 v = { if (i(Vsense1) < 0, 0, if( i(Vsense1) > 0.02, 1, { i(Vsense1) / 0.02 })) }

dd2 A2 0vNode2 ledDiodeModel
Vsense2 0vNode2 K DC 0
* Interactive sense node
b2 lit2 0 v = { if (i(Vsense2) < 0, 0, if( i(Vsense2) > 0.02, 1, { i(Vsense2) / 0.02 })) }

dd3 A3 0vNode3 ledDiodeModel
Vsense3 0vNode3 K DC 0
* Interactive sense node
b3 lit3 0 v = { if (i(Vsense3) < 0, 0, if( i(Vsense3) > 0.02, 1, { i(Vsense3) / 0.02 })) }

dd4 A4 0vNode4 ledDiodeModel
Vsense4 0vNode4 K DC 0
* Interactive sense node
b4 lit4 0 v = { if (i(Vsense4) < 0, 0, if( i(Vsense4) > 0.02, 1, { i(Vsense4) / 0.02 })) }

dd5 A5 0vNode5 ledDiodeModel
Vsense5 0vNode5 K DC 0
* Interactive sense node
b5 lit5 0 v = { if (i(Vsense5) < 0, 0, if( i(Vsense5) > 0.02, 1, { i(Vsense5) / 0.02 })) }

dd6 A6 0vNode6 ledDiodeModel
Vsense6 0vNode6 K DC 0
* Interactive sense node
b6 lit6 0 v = { if (i(Vsense6) < 0, 0, if( i(Vsense6) > 0.02, 1, { i(Vsense6) / 0.02 })) }

dd7 A7 0vNode7 ledDiodeModel
Vsense7 0vNode7 K DC 0
* Interactive sense node
b7 lit7 0 v = { if (i(Vsense7) < 0, 0, if( i(Vsense7) > 0.02, 1, { i(Vsense7) / 0.02 })) }

.model ledDiodeModel D( IS=1e-14 N=1 RS=0 IBV=1e-10 BV=1e+30 CJO=0 M=0.5 VJ=1 )
.ends

* --- Pin bridge models

.SUBCKT REAL_CUSTOM_ADC 1 2 PARAMS: lowV=0 maxLowV=0.8 unknownV=1.0 minHighV=2.0 highV=5.0 riseT=0 fallT=0
* Ideal Receiver Model 1 = input, 2 = A/D out
aADCin1 [2] [1] ADC
.MODEL ADC adc_bridge (in_low = {maxLowV} in_high = {minHighV})
.ENDS

.SUBCKT REAL_CUSTOM_DAC 1 2 PARAMS: lowV=0 maxLowV=0.8 unknownV=1.0 minHighV=2.0 highV=5.0 riseT=0 fallT=0
* Ideal Driver Model 1 = A/D out, 2 = input
aDACin1 [1] [2] aDAC
.MODEL aDAC dac_bridge (out_low = {lowV} out_high = {highV} out_undef = {unknownV} t_rise = {max(riseT,1e-9)} t_fall = {max(fallT,1e-9)})
.ENDS

Errors and Warnings

Any error, warning or information messages appear below.

Item

Document

Section

Only one section is available for multisection components.

Type

Rise time

Time it takes for signal to transition from low to high.

With non-zero rise time, the signal converts to an analog signal from a digital signal.

Fall time

Time it takes for signal to transition from high to low.

With non-zero fall time, the signal converts to an analog signal from a digital signal.

Use document settings

Use logic levels settings from Document tab.

Threshold voltage levels.

Threshold voltage values used in the logic evaluation. See Digital Simulation for more information.

Output low

Output low voltage.

Maximum output voltage level to produce a low signal.

Input low threshold

Input low threshold voltage.

Maximum input voltage level for the signal to be considered low.

Input high threshold

Input high threshold voltage.

Minimum input voltage level for the signal to be considered high.

Output high

Output high voltage.

Minimum output voltage level to produce a high signal.

Type Probe

Select desired function.

Function

Use document settings

Use logic levels settings from Document tab.

Threshold voltage levels.

Threshold voltage values used in the logic evaluation. See Digital Simulation for more information.

Output low

Output low voltage.

Maximum output voltage level to produce a low signal.

Input low threshold

Input low threshold voltage.

Maximum input voltage level for the signal to be considered low.

Input high threshold

Input high threshold voltage.

Minimum input voltage level for the signal to be considered high.

Output high

Output high voltage.

Minimum output voltage level to produce a high signal.

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Available functions, constants and operators for the expression.

Source

Data origin.

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Web address of the selected Source.

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Connect

Cancel

Connecting

Disconnect

Switch on to stream data from Source when simulation runs.

For data files with more than one plot, select the plot to view.

Source type

Application used to generate the Source data.

Data type

Type of simulation data in Source.

File size

Size of the referenced file. Total file size for all data plotters cannot exceed 100 MB.

Selected simulation type does not match uploaded simulation data

Data streaming is only available in interactive simulation

Instantaneous

Displays instantaneous measurements on probe during interactive simulation.

Periodic

Displays periodic measurements on probe during Interactive simulation.

Bias point(s)

Displays bias points on probe for DC Op simulation.

No items selected.

Name 3.2.4 Asynchronous Counters Now Serving Display

Type Schematic

The simulation to run. See Simulation types for more information.

Name

Title of graph. Edit as desired.

End time

Time at which the simulation stops. Does not include pauses. Simulation does not occur in real time.

Start simulation

RELTOL

Relative error tolerance. A simulation wide accuracy control used to establish convergence.

VNTOL

Absolute voltage error tolerance. Defines the minimum value for voltage where it may still be considered accurate.

ABSTOL

Absolute current error tolerance. Defines the minimum value for current where it may still be considered accurate.

ITL1

DC iteration limit. Number of iterative passes done on DC circuit equations in attempt to reach convergence in simulation.

ITL4

Upper iteration limit. Number of iterative passes done per time point, on Transient circuit equations in attempt to reach convergence in simulation.

Integration method. The numerical integration method used in transient analysis.

Temp

℃

Operating temperature. The temperature at which the entire circuit will be simulated.

Insert shunt resistance

Inserts a resistance of RSHUNT from every analog node to ground. Will aid in convergence, but alter the behavior of the circuit.

RSHUNT

Shunt resistance. This eliminates singular matrix errors that result from a lack of a DC path to ground.

Reset to default

Threshold voltage levels.

Threshold voltage values used in the logic evaluation. See Digital Simulation for more information.

Output low

Output low voltage.

Maximum output voltage level to produce a low signal.

Input low threshold

Input low threshold voltage.

Maximum input voltage level for the signal to be considered low.

Input high threshold

Input high threshold voltage.

Minimum input voltage level for the signal to be considered high.

Output high

Output high voltage.

Minimum output voltage level to produce a high signal.

Width

Sheet width in grid squares.

Height

Sheet height in grid squares.

Grid

Toggles grid display.

Net Labels

Toggles all net labels.

Component Labels

Toggles all component labels.

3.2.4 Asynchronous Counters Now Serving Display