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U1U2U3U4InputCLK120LED103U5U6U7456U8U9U10U11U12U13789101112131415Input1U141617input218Input319input420PR1PR2PR3PR4 0/1 0/1 V V
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ID:

ID:

x10
x0.1
Sheet:1
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Details
Netlist
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SPICE
SPICE Netlist

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** PISO **
*
* Multisim Live SPICE netlist
*
*

* --- Circuit Topology ---

* Component: CLK
aCLK 2 Digital_Source_CLK

* Component: Input
aInput 1 Digital_Source_Input

* Component: Input1
aInput1 17 Digital_Source_Input1

* Component: Input3
aInput3 19 Digital_Source_Input3

* Component: LED1
xLED1 3 0 LED_VIRTUAL_LED1

* Component: U1
aU1 1 2 U1_NC_SET bridgeU1!RESET 13 U1_NC_~Q Digital_DFlipFlopPOSSR_U1

xbridgeU1!RESET bridgeU1!RESET 0 REAL_CUSTOM_ADC PARAMS: lowV=0 maxLowV=0.8 unknownV=1 minHighV=2 highV=5 riseT=0 fallT=0

* Component: U10
aU10 [17 14] 9 Digital_AND2_U10

* Component: U11
aU11 [19 16] 10 Digital_AND2_U11

* Component: U12
aU12 [17 bridgeU12!B] 11 Digital_AND2_U12

xbridgeU12!B bridgeU12!B 15 REAL_CUSTOM_ADC PARAMS: lowV=0 maxLowV=0.8 unknownV=1 minHighV=2 highV=5 riseT=0 fallT=0

* Component: U13
aU13 [20 16] 12 Digital_AND2_U13

* Component: U14
aU14 17 16 Digital_Inverter_U14

* Component: U2
aU2 4 2 U2_NC_SET bridgeU2!RESET 14 U2_NC_~Q Digital_DFlipFlopPOSSR_U2

xbridgeU2!RESET bridgeU2!RESET 0 REAL_CUSTOM_ADC PARAMS: lowV=0 maxLowV=0.8 unknownV=1 minHighV=2 highV=5 riseT=0 fallT=0

* Component: U3
aU3 5 2 U3_NC_SET bridgeU3!RESET bridgeU3!Q U3_NC_~Q Digital_DFlipFlopPOSSR_U3

xbridgeU3!RESET bridgeU3!RESET 0 REAL_CUSTOM_ADC PARAMS: lowV=0 maxLowV=0.8 unknownV=1 minHighV=2 highV=5 riseT=0 fallT=0

xbridgeU3!Q bridgeU3!Q 15 REAL_CUSTOM_DAC PARAMS: lowV=0 maxLowV=0.8 unknownV=1 minHighV=2 highV=5 riseT=0 fallT=0

* Component: U4
aU4 6 2 U4_NC_SET bridgeU4!RESET bridgeU4!Q U4_NC_~Q Digital_DFlipFlopPOSSR_U4

xbridgeU4!RESET bridgeU4!RESET 0 REAL_CUSTOM_ADC PARAMS: lowV=0 maxLowV=0.8 unknownV=1 minHighV=2 highV=5 riseT=0 fallT=0

xbridgeU4!Q bridgeU4!Q 3 REAL_CUSTOM_DAC PARAMS: lowV=0 maxLowV=0.8 unknownV=1 minHighV=2 highV=5 riseT=0 fallT=0

* Component: U5
aU5 [8 7] 4 Digital_OR2_U5

* Component: U6
aU6 [10 9] 5 Digital_OR2_U6

* Component: U7
aU7 [12 11] 6 Digital_OR2_U7

* Component: U8
aU8 [17 13] 7 Digital_AND2_U8

* Component: U9
aU9 [18 16] 8 Digital_AND2_U9

* Component: input2
ainput2 18 Digital_Source_input2

* Component: input4
ainput4 20 Digital_Source_input4


* --- Circuit Models ---

* CLK model
.model Digital_Source_CLK d_constsource(State=1)

* Input model
.model Digital_Source_Input d_constsource(State=1)

* Input1 model
.model Digital_Source_Input1 d_constsource(State=1)

* Input3 model
.model Digital_Source_Input3 d_constsource(State=1)

* U1 model
.model Digital_DFlipFlopPOSSR_U1 d_dff (rise_delay=1e-9 fall_delay=1e-9 clk_delay=1e-9 set_delay=1e-9 reset_delay=1e-9 ic=0)

* U10 model
.model Digital_AND2_U10 d_and (rise_delay=1e-9 fall_delay=1e-9)

* U11 model
.model Digital_AND2_U11 d_and (rise_delay=1e-9 fall_delay=1e-9)

* U12 model
.model Digital_AND2_U12 d_and (rise_delay=1e-9 fall_delay=1e-9)

* U13 model
.model Digital_AND2_U13 d_and (rise_delay=1e-9 fall_delay=1e-9)

* U14 model
.model Digital_Inverter_U14 d_inverter (rise_delay=1e-9 fall_delay=1e-9)

* U2 model
.model Digital_DFlipFlopPOSSR_U2 d_dff (rise_delay=1e-9 fall_delay=1e-9 clk_delay=1e-9 set_delay=1e-9 reset_delay=1e-9 ic=0)

* U3 model
.model Digital_DFlipFlopPOSSR_U3 d_dff (rise_delay=1e-9 fall_delay=1e-9 clk_delay=1e-9 set_delay=1e-9 reset_delay=1e-9 ic=0)

* U4 model
.model Digital_DFlipFlopPOSSR_U4 d_dff (rise_delay=1e-9 fall_delay=1e-9 clk_delay=1e-9 set_delay=1e-9 reset_delay=1e-9 ic=0)

* U5 model
.model Digital_OR2_U5 d_or (rise_delay=1e-9 fall_delay=1e-9)

* U6 model
.model Digital_OR2_U6 d_or (rise_delay=1e-9 fall_delay=1e-9)

* U7 model
.model Digital_OR2_U7 d_or (rise_delay=1e-9 fall_delay=1e-9)

* U8 model
.model Digital_AND2_U8 d_and (rise_delay=1e-9 fall_delay=1e-9)

* U9 model
.model Digital_AND2_U9 d_and (rise_delay=1e-9 fall_delay=1e-9)

* input2 model
.model Digital_Source_input2 d_constsource(State=1)

* input4 model
.model Digital_Source_input4 d_constsource(State=1)


* --- Subcircuits ---

* LED1 subcircuit
.subckt LED_VIRTUAL_LED1 A K

dd1 A 0vNode ledDiodeModel
.model ledDiodeModel D( IS=1e-14 N=1 RS=0 IBV=1e-10 BV=1e+30 CJO=0 M=0.5 VJ=1 )

V_Isense 0vNode K DC 0

* Interactive sense node
b1 lit 0 v = { if (i(V_Isense) < 0, 0, if( i(V_Isense) > 0.005, 1, { i(V_Isense) / 0.005 })) }

.ends


* --- Pin bridge models

.SUBCKT REAL_CUSTOM_ADC 1 2 PARAMS: lowV=0 maxLowV=0.8 unknownV=1.0 minHighV=2.0 highV=5.0 riseT=0 fallT=0
* Ideal Receiver Model 1 = input, 2 = A/D out
aADCin1 [2] [1] ADC
.MODEL ADC adc_bridge (in_low = {maxLowV} in_high = {minHighV})
.ENDS

.SUBCKT REAL_CUSTOM_DAC 1 2 PARAMS: lowV=0 maxLowV=0.8 unknownV=1.0 minHighV=2.0 highV=5.0 riseT=0 fallT=0
* Ideal Driver Model 1 = A/D out, 2 = input
aDACin1 [1] [2] aDAC
.MODEL aDAC dac_bridge (out_low = {lowV} out_high = {highV} out_undef = {unknownV} t_rise = {max(riseT,1e-9)} t_fall = {max(fallT,1e-9)})
.ENDS
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PISO
Schematic

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Name

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End time

s

Time at which the simulation stops. Does not include pauses. Simulation does not occur in real time.

Start simulation

Mode

Threshold voltage levels.

Threshold voltage values used in the logic evaluation. See Digital Simulation for more information.

Output low

V

Output low voltage.

Maximum output voltage level to produce a low signal.

Input low threshold

V

Input low threshold voltage.

Maximum input voltage level for the signal to be considered low.

Input high threshold

V

Input high threshold voltage.

Minimum input voltage level for the signal to be considered high.

Output high

V

Output high voltage.

Minimum output voltage level to produce a high signal.

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