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ID:

ID:
x10
x0.1
Sheet:1
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SPICE
SPICE Netlist

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** PISO **
*
* Multisim Live SPICE netlist
*
*

* --- Circuit Topology ---

* Component: CLK
aCLK 2 Digital_Source_CLK

* Component: INPUT
aINPUT 1 Digital_Source_INPUT

* Component: INPUT1
aINPUT1 18 Digital_Source_INPUT1

* Component: INPUT2
aINPUT2 15 Digital_Source_INPUT2

* Component: INPUT3
aINPUT3 16 Digital_Source_INPUT3

* Component: INPUT4
aINPUT4 17 Digital_Source_INPUT4

* Component: LED1
xLED1 20 0 LED_VIRTUAL_LED1

* Component: U1
aU1 [6 5] 4 Digital_OR2_U1

* Component: U10
aU10 [18 14] 7 Digital_AND2_U10

* Component: U11
aU11 [16 19] 8 Digital_AND2_U11

* Component: U12
aU12 [18 11] 9 Digital_AND2_U12

* Component: U13
aU13 [17 19] 10 Digital_AND2_U13

* Component: U14
aU14 18 19 Digital_Inverter_U14

* Component: U2
xU2 1 2 U2_NC_SET bridgeU2!RESET 3 U2_NC_~Q Digital_DFlipFlop_U2 PARAMS: Negative_Edge_Clock=0 Negative_SET_RESET=0 Rise_delay=1e-9 Fall_delay=1e-9 Clk_delay=1e-9 Set_delay=1e-9 Reset_delay=1e-9 Ic=0

xbridgeU2!RESET bridgeU2!RESET 0 REAL_CUSTOM_ADC PARAMS: lowV=0 maxLowV=0.8 unknownV=1 minHighV=2 highV=5 riseT=0 fallT=0

* Component: U3
xU3 4 2 U3_NC_SET bridgeU3!RESET 14 U3_NC_~Q Digital_DFlipFlop_U3 PARAMS: Negative_Edge_Clock=0 Negative_SET_RESET=0 Rise_delay=1e-9 Fall_delay=1e-9 Clk_delay=1e-9 Set_delay=1e-9 Reset_delay=1e-9 Ic=0

xbridgeU3!RESET bridgeU3!RESET 0 REAL_CUSTOM_ADC PARAMS: lowV=0 maxLowV=0.8 unknownV=1 minHighV=2 highV=5 riseT=0 fallT=0

* Component: U4
xU4 13 2 U4_NC_SET bridgeU4!RESET 11 U4_NC_~Q Digital_DFlipFlop_U4 PARAMS: Negative_Edge_Clock=0 Negative_SET_RESET=0 Rise_delay=1e-9 Fall_delay=1e-9 Clk_delay=1e-9 Set_delay=1e-9 Reset_delay=1e-9 Ic=0

xbridgeU4!RESET bridgeU4!RESET 0 REAL_CUSTOM_ADC PARAMS: lowV=0 maxLowV=0.8 unknownV=1 minHighV=2 highV=5 riseT=0 fallT=0

* Component: U5
xU5 12 2 U5_NC_SET bridgeU5!RESET bridgeU5!Q U5_NC_~Q Digital_DFlipFlop_U5 PARAMS: Negative_Edge_Clock=0 Negative_SET_RESET=0 Rise_delay=1e-9 Fall_delay=1e-9 Clk_delay=1e-9 Set_delay=1e-9 Reset_delay=1e-9 Ic=0

xbridgeU5!RESET bridgeU5!RESET 0 REAL_CUSTOM_ADC PARAMS: lowV=0 maxLowV=0.8 unknownV=1 minHighV=2 highV=5 riseT=0 fallT=0

xbridgeU5!Q bridgeU5!Q 20 REAL_CUSTOM_DAC PARAMS: lowV=0 maxLowV=0.8 unknownV=1 minHighV=2 highV=5 riseT=0 fallT=0

* Component: U6
aU6 [8 7] 13 Digital_OR2_U6

* Component: U7
aU7 [10 9] 12 Digital_OR2_U7

* Component: U8
aU8 [18 3] 5 Digital_AND2_U8

* Component: U9
aU9 [15 19] 6 Digital_AND2_U9


* --- Circuit Models ---

* CLK model
.model Digital_Source_CLK d_constsource(State=1)

* INPUT model
.model Digital_Source_INPUT d_constsource(State=0)

* INPUT1 model
.model Digital_Source_INPUT1 d_constsource(State=1)

* INPUT2 model
.model Digital_Source_INPUT2 d_constsource(State=1)

* INPUT3 model
.model Digital_Source_INPUT3 d_constsource(State=0)

* INPUT4 model
.model Digital_Source_INPUT4 d_constsource(State=1)

* U1 model
.model Digital_OR2_U1 d_or (rise_delay=1e-9 fall_delay=1e-9)

* U10 model
.model Digital_AND2_U10 d_and (rise_delay=1e-9 fall_delay=1e-9)

* U11 model
.model Digital_AND2_U11 d_and (rise_delay=1e-9 fall_delay=1e-9)

* U12 model
.model Digital_AND2_U12 d_and (rise_delay=1e-9 fall_delay=1e-9)

* U13 model
.model Digital_AND2_U13 d_and (rise_delay=1e-9 fall_delay=1e-9)

* U14 model
.model Digital_Inverter_U14 d_inverter (rise_delay=1e-9 fall_delay=1e-9)

* U6 model
.model Digital_OR2_U6 d_or (rise_delay=1e-9 fall_delay=1e-9)

* U7 model
.model Digital_OR2_U7 d_or (rise_delay=1e-9 fall_delay=1e-9)

* U8 model
.model Digital_AND2_U8 d_and (rise_delay=1e-9 fall_delay=1e-9)

* U9 model
.model Digital_AND2_U9 d_and (rise_delay=1e-9 fall_delay=1e-9)


* --- Subcircuits ---

* LED1 subcircuit
.subckt LED_VIRTUAL_LED1 A K

dd1 A 0vNode ledDiodeModel
.model ledDiodeModel D( IS=1e-14 N=1 RS=0 IBV=1e-10 BV=1e+30 CJO=0 M=0.5 VJ=1 )

V_Isense 0vNode K DC 0

* Interactive sense node
b1 lit 0 v = { if (i(V_Isense) < 0, 0, if( i(V_Isense) > 0.005, 1, { i(V_Isense) / 0.005 })) }

.ends

* U2 subcircuit
.subckt Digital_DFlipFlop_U2 1 2 3 4 5 6 PARAMS: Negative_Edge_Clock=0 Negative_SET_RESET=0 Clk_delay=1n Set_delay=1n Reset_delay=1n Ic=0 Rise_delay=1n Fall_delay=1n
*PIN MAPPING: D Q ~Q RESET CLK SET
* 1 5 6 4 2 3
*MODELS USED
aDG1 neg_SR Digital_SourceSR
aDG2 neg_clk Digital_SourceCLK
Axor1 [3 neg_SR] set xor
Axor2 [2 neg_clk] clk xor
Axor3 [4 neg_SR] reset xor
Ajkff 1 clk set reset 5 6 D_FF

.model Digital_SourceCLK d_constsource(State={Negative_Edge_Clock})
.model Digital_SourceSR d_constsource(State={Negative_SET_RESET})
.model xor d_xor
.MODEL D_FF d_dff (clk_delay={Clk_delay} set_delay={Set_delay} reset_delay={Reset_delay} ic={Ic} rise_delay={Rise_delay} fall_delay={Fall_delay})
.ENDS

* U3 subcircuit
.subckt Digital_DFlipFlop_U3 1 2 3 4 5 6 PARAMS: Negative_Edge_Clock=0 Negative_SET_RESET=0 Clk_delay=1n Set_delay=1n Reset_delay=1n Ic=0 Rise_delay=1n Fall_delay=1n
*PIN MAPPING: D Q ~Q RESET CLK SET
* 1 5 6 4 2 3
*MODELS USED
aDG1 neg_SR Digital_SourceSR
aDG2 neg_clk Digital_SourceCLK
Axor1 [3 neg_SR] set xor
Axor2 [2 neg_clk] clk xor
Axor3 [4 neg_SR] reset xor
Ajkff 1 clk set reset 5 6 D_FF

.model Digital_SourceCLK d_constsource(State={Negative_Edge_Clock})
.model Digital_SourceSR d_constsource(State={Negative_SET_RESET})
.model xor d_xor
.MODEL D_FF d_dff (clk_delay={Clk_delay} set_delay={Set_delay} reset_delay={Reset_delay} ic={Ic} rise_delay={Rise_delay} fall_delay={Fall_delay})
.ENDS

* U4 subcircuit
.subckt Digital_DFlipFlop_U4 1 2 3 4 5 6 PARAMS: Negative_Edge_Clock=0 Negative_SET_RESET=0 Clk_delay=1n Set_delay=1n Reset_delay=1n Ic=0 Rise_delay=1n Fall_delay=1n
*PIN MAPPING: D Q ~Q RESET CLK SET
* 1 5 6 4 2 3
*MODELS USED
aDG1 neg_SR Digital_SourceSR
aDG2 neg_clk Digital_SourceCLK
Axor1 [3 neg_SR] set xor
Axor2 [2 neg_clk] clk xor
Axor3 [4 neg_SR] reset xor
Ajkff 1 clk set reset 5 6 D_FF

.model Digital_SourceCLK d_constsource(State={Negative_Edge_Clock})
.model Digital_SourceSR d_constsource(State={Negative_SET_RESET})
.model xor d_xor
.MODEL D_FF d_dff (clk_delay={Clk_delay} set_delay={Set_delay} reset_delay={Reset_delay} ic={Ic} rise_delay={Rise_delay} fall_delay={Fall_delay})
.ENDS

* U5 subcircuit
.subckt Digital_DFlipFlop_U5 1 2 3 4 5 6 PARAMS: Negative_Edge_Clock=0 Negative_SET_RESET=0 Clk_delay=1n Set_delay=1n Reset_delay=1n Ic=0 Rise_delay=1n Fall_delay=1n
*PIN MAPPING: D Q ~Q RESET CLK SET
* 1 5 6 4 2 3
*MODELS USED
aDG1 neg_SR Digital_SourceSR
aDG2 neg_clk Digital_SourceCLK
Axor1 [3 neg_SR] set xor
Axor2 [2 neg_clk] clk xor
Axor3 [4 neg_SR] reset xor
Ajkff 1 clk set reset 5 6 D_FF

.model Digital_SourceCLK d_constsource(State={Negative_Edge_Clock})
.model Digital_SourceSR d_constsource(State={Negative_SET_RESET})
.model xor d_xor
.MODEL D_FF d_dff (clk_delay={Clk_delay} set_delay={Set_delay} reset_delay={Reset_delay} ic={Ic} rise_delay={Rise_delay} fall_delay={Fall_delay})
.ENDS


* --- Pin bridge models

.SUBCKT REAL_CUSTOM_ADC 1 2 PARAMS: lowV=0 maxLowV=0.8 unknownV=1.0 minHighV=2.0 highV=5.0 riseT=0 fallT=0
* Ideal Receiver Model 1 = input, 2 = A/D out
aADCin1 [2] [1] ADC
.MODEL ADC adc_bridge (in_low = {maxLowV} in_high = {minHighV})
.ENDS

.SUBCKT REAL_CUSTOM_DAC 1 2 PARAMS: lowV=0 maxLowV=0.8 unknownV=1.0 minHighV=2.0 highV=5.0 riseT=0 fallT=0
* Ideal Driver Model 1 = A/D out, 2 = input
aDACin1 [1] [2] aDAC
.MODEL aDAC dac_bridge (out_low = {lowV} out_high = {highV} out_undef = {unknownV} t_rise = {max(riseT,1e-9)} t_fall = {max(fallT,1e-9)})
.ENDS
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Output low

V
Output low voltage.

Maximum output voltage level to produce a low signal.

Input low threshold

V
Input low threshold voltage.

Maximum input voltage level for the signal to be considered low.

Input high threshold

V
Input high threshold voltage.

Minimum input voltage level for the signal to be considered high.

Output high

V
Output high voltage.

Minimum output voltage level to produce a high signal.

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