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αPh+T1Ph-T2 120V60Hz-45°V1U1SCR_ASCR_B121ΩR1R21Ω1uHL1L21uH3456745VV28SCR_BV3120V60Hz135°9 VA
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x10
x0.1
Sheet:1
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** EEE_174 LAB2 **
*
* Multisim Live SPICE netlist
*
*

* --- Circuit Topology ---

* Component: L1
lL1 6 0 0.000001

* Component: L2
lL2 7 0 0.000001

* Component: R1
rR1 4 6 1 VIRTUAL_RESISTANCE_R1

* Component: R2
rR2 5 7 1 VIRTUAL_RESISTANCE_R2

* Component: SCR_A
xSCR_A 3 4 1 SCR_IDEAL_SCR_A PARAMS: Vth=2.5 Ih=0.01 Vfscr=0 Ron=0.01 Roff=10000000

* Component: SCR_B
xSCR_B 9 5 2 SCR_IDEAL_SCR_B PARAMS: Vth=2.5 Ih=0.01 Vfscr=0 Ron=0.01 Roff=10000000

* Component: U1
xU1 3 0 8 1 2 PHASEANGLE_FULL_U1 PARAMS: frequency=60 pulse_width=20 pulse_amplitude=120

* Component: V1
vV1 3 0 dc 0 ac 1 0
+ distof1 0 0
+ distof2 0 0
+ sin ( 0 120 60 0 0 -45 )

* Component: V2
vV2 8 0 dc 45 ac 0 0
+ distof1 0 0
+ distof2 0 0

* Component: V3
vV3 9 0 dc 0 ac 1 0
+ distof1 0 0
+ distof2 0 0
+ sin ( 0 120 60 0 0 135 )


* --- Circuit Models ---

* R1 model
.model VIRTUAL_RESISTANCE_R1 r( )

* R2 model
.model VIRTUAL_RESISTANCE_R2 r( )


* --- Subcircuits ---

* SCR_A subcircuit
.subckt SCR_IDEAL_SCR_A Anode Cathode Gate PARAMS: Vth=2.5 Ih=0 Vfscr=0 Ron=1m Roff=1meg
E3 a2 0 Value = { if(I(vIscr)<=Ih,5,0) }

vIscr Anode 10 dc 0



xU6 8 cathode DIODE_IDEAL params: Vf={Vfscr} Rd={Ron/2} Rdoff={Roff/2}
.subckt DIODE_IDEAL a k params: Vf=0 Rd=1m Rdoff=1meg
ad1 %vd(a k) %id(a k) diode1
.model diode1 pwl(x_array=[{Vf-1} {Vf} {Vf+1}] y_array=[{-1/Rdoff} 0 {1/Rd}] fraction=false input_domain=0.0)
.ends


xS1 10 8 a3 0 VSwitchS1
.subckt VSwitchS1 1 2 3 4
S1 1 2 3 4 vsw0
.model vsw0 vswitch ( Roff={Roff/2} Ron={Ron/2} Voff=0 Von=1 )
.ends


aU5 7 d_constsource_U5
.model d_constsource_U5 d_constsource(state=1)


aU4 [a1 dU4.B dU4.C] reset AND2__TIL__1
xU4.B a2 dU4.B TIL_RCV__NON__1
xU4.C a3 dU4.C TIL_RCV__NON__1
aU3 dU3.A a1 NOT__TIL__1

xU3.A gate dU3.A TIL_RCV__NON__1_Gate

aU2 dU2.S reset 7
+ U2_OPEN_SET U2_OPEN_RESET
+ dU2.Q U2_OPEN_notQ SR_LATCH__TIL__1

xU2.S gate dU2.S TIL_RCV__NON__1_Gate


xU2.Q dU2.Q a3 TIL_DRV__NON__1



.MODEL AND2__TIL__1 d_and ( rise_delay = 1n fall_delay = 1n)
.MODEL NOT__TIL__1 d_inverter (rise_delay = 1n fall_delay = 1n)
.SUBCKT TIL_DRV__NON__1 1 2
* TIL Driver Model 1 = D/A input, 2 = out
aDACin1 [1] [2] aDAC
.MODEL aDAC dac_bridge (out_low= 0 out_high = 5 out_undef = 0)
.ENDS

.SUBCKT TIL_RCV__NON__1_Gate 1 2
* TIL Receiver Model 1 = input, 2 = A/D out
aADCin1 [1] [2] ADC
.MODEL ADC adc_bridge (in_low= {Vth} in_high = {Vth})
.ENDS

.SUBCKT TIL_RCV__NON__1 1 2
* TIL Receiver Model 1 = input, 2 = A/D out
aADCin1 [1] [2] ADC
.MODEL ADC adc_bridge (in_low= 2.5 in_high = 2.5)
.ENDS


.MODEL SR_LATCH__TIL__1 d_srlatch (sr_delay = 1n enable_delay = 1n
+ set_delay = 1n reset_delay= 1n
+ ic = 0 rise_delay = 1n fall_delay = 1n)

.ends

* SCR_B subcircuit
.subckt SCR_IDEAL_SCR_B Anode Cathode Gate PARAMS: Vth=2.5 Ih=0 Vfscr=0 Ron=1m Roff=1meg
E3 a2 0 Value = { if(I(vIscr)<=Ih,5,0) }

vIscr Anode 10 dc 0



xU6 8 cathode DIODE_IDEAL params: Vf={Vfscr} Rd={Ron/2} Rdoff={Roff/2}
.subckt DIODE_IDEAL a k params: Vf=0 Rd=1m Rdoff=1meg
ad1 %vd(a k) %id(a k) diode1
.model diode1 pwl(x_array=[{Vf-1} {Vf} {Vf+1}] y_array=[{-1/Rdoff} 0 {1/Rd}] fraction=false input_domain=0.0)
.ends


xS1 10 8 a3 0 VSwitchS1
.subckt VSwitchS1 1 2 3 4
S1 1 2 3 4 vsw0
.model vsw0 vswitch ( Roff={Roff/2} Ron={Ron/2} Voff=0 Von=1 )
.ends


aU5 7 d_constsource_U5
.model d_constsource_U5 d_constsource(state=1)


aU4 [a1 dU4.B dU4.C] reset AND2__TIL__1
xU4.B a2 dU4.B TIL_RCV__NON__1
xU4.C a3 dU4.C TIL_RCV__NON__1
aU3 dU3.A a1 NOT__TIL__1

xU3.A gate dU3.A TIL_RCV__NON__1_Gate

aU2 dU2.S reset 7
+ U2_OPEN_SET U2_OPEN_RESET
+ dU2.Q U2_OPEN_notQ SR_LATCH__TIL__1

xU2.S gate dU2.S TIL_RCV__NON__1_Gate


xU2.Q dU2.Q a3 TIL_DRV__NON__1



.MODEL AND2__TIL__1 d_and ( rise_delay = 1n fall_delay = 1n)
.MODEL NOT__TIL__1 d_inverter (rise_delay = 1n fall_delay = 1n)
.SUBCKT TIL_DRV__NON__1 1 2
* TIL Driver Model 1 = D/A input, 2 = out
aDACin1 [1] [2] aDAC
.MODEL aDAC dac_bridge (out_low= 0 out_high = 5 out_undef = 0)
.ENDS

.SUBCKT TIL_RCV__NON__1_Gate 1 2
* TIL Receiver Model 1 = input, 2 = A/D out
aADCin1 [1] [2] ADC
.MODEL ADC adc_bridge (in_low= {Vth} in_high = {Vth})
.ENDS

.SUBCKT TIL_RCV__NON__1 1 2
* TIL Receiver Model 1 = input, 2 = A/D out
aADCin1 [1] [2] ADC
.MODEL ADC adc_bridge (in_low= 2.5 in_high = 2.5)
.ENDS


.MODEL SR_LATCH__TIL__1 d_srlatch (sr_delay = 1n enable_delay = 1n
+ set_delay = 1n reset_delay= 1n
+ ic = 0 rise_delay = 1n fall_delay = 1n)

.ends

* U1 subcircuit
.subckt PHASEANGLE_FULL_U1 sync+ sync- alpha T1 T2 PARAMS: frequency=1 pulse_width=1 pulse_amplitude=1
AT1 %vd(sync+,sync-) alpha %vd(T1,0) alphamod


E1 alpha2 0 value={v(alpha)+180}
AT3 %vd(sync+,sync-) alpha2 %vd(T2,0) alphamod

.model alphamod phase_angle_controller(freq={frequency} pulse_width={pulse_width} pulse_amplitude={pulse_amplitude})
.ends
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EEE_174 LAB2
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Input low threshold voltage.

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Input high threshold

V
Input high threshold voltage.

Minimum input voltage level for the signal to be considered high.

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Output high voltage.

Minimum output voltage level to produce a high signal.

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