*single phase half wave controlled rectifier(from 0 to 90 degree)

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Cursor 1	Cursor 2	∆X	1/∆X	∆Y	∆Y (Phase)

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x10

x0.1

Sheet:1

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SPICE

SPICE Netlist

This is a text-based representation of the circuit.
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** single phase half wave controlled rectifier(from 0 to 90 degree) **
*
* Multisim Live SPICE netlist
*
*

* --- Circuit Topology ---

* Component: D1
dD1 7 8 1N4148_2_D1

* Component: D2
dD2 1 2 1N4148_2_D2

* Component: D3
dD3 11 12 1N4148_2_D3

* Component: D4
dD4 16 13 1N4148_2_D4

* Component: D5
dD5 D5_NC_A 14 1N4148_2_D5

* Component: D6
dD6 16 15 1N4148_2_D6

* Component: R1
rR1 13 5 1000 VIRTUAL_RESISTANCE_R1

* Component: R10
rR10 16 10 1000 VIRTUAL_RESISTANCE_R10

* Component: R2
rR2 17 16 1000 VIRTUAL_RESISTANCE_R2

* Component: R3
xR3 5 7 3 Potentiometer_R3 PARAMS: res=50000 posPercent=100

* Component: R4
rR4 14 4 1000 VIRTUAL_RESISTANCE_R4

* Component: R5
xR5 4 1 6 Potentiometer_R5 PARAMS: res=50000 posPercent=100

* Component: R6
rR6 16 6 1000 VIRTUAL_RESISTANCE_R6

* Component: R7
rR7 15 9 1000 VIRTUAL_RESISTANCE_R7

* Component: R8
xR8 9 11 10 Potentiometer_R8 PARAMS: res=50000 posPercent=100

* Component: R9
rR9 16 3 1000 VIRTUAL_RESISTANCE_R9

* Component: SCR_A1
xSCR_A1 13 17 8 SCR_IDEAL_SCR_A1 PARAMS: Vth=1 Ih=0 Vfscr=0 Ron=0.01 Roff=10000000

* Component: SCR_A2
xSCR_A2 14 SCR_A2_NC_K 2 SCR_IDEAL_SCR_A2 PARAMS: Vth=1 Ih=0 Vfscr=0 Ron=0.01 Roff=10000000

* Component: SCR_A3
xSCR_A3 15 SCR_A3_NC_K 12 SCR_IDEAL_SCR_A3 PARAMS: Vth=1 Ih=0 Vfscr=0 Ron=0.01 Roff=10000000

* Component: V1
xV1 V1_NC_1 14 V1_NC_3 3PHDELTA_V1 PARAMS: vrms=120 freq=60 td=0 damp=0

* --- Circuit Models ---

* D1 model
.model 1N4148_2_D1 d (
+ IS=6.89131e-09 RS=0.636257 N=1.82683 EG=1.15805
+ XTI=0.518861 BV=80 IBV=0.0001 CJO=9.99628e-13
+ VJ=0.942987 M=0.727538 FC=0.5 TT=4.33674e-09
+ KF=0 AF=1 )

* D2 model
.model 1N4148_2_D2 d (
+ IS=6.89131e-09 RS=0.636257 N=1.82683 EG=1.15805
+ XTI=0.518861 BV=80 IBV=0.0001 CJO=9.99628e-13
+ VJ=0.942987 M=0.727538 FC=0.5 TT=4.33674e-09
+ KF=0 AF=1 )

* D3 model
.model 1N4148_2_D3 d (
+ IS=6.89131e-09 RS=0.636257 N=1.82683 EG=1.15805
+ XTI=0.518861 BV=80 IBV=0.0001 CJO=9.99628e-13
+ VJ=0.942987 M=0.727538 FC=0.5 TT=4.33674e-09
+ KF=0 AF=1 )

* D4 model
.model 1N4148_2_D4 d (
+ IS=6.89131e-09 RS=0.636257 N=1.82683 EG=1.15805
+ XTI=0.518861 BV=80 IBV=0.0001 CJO=9.99628e-13
+ VJ=0.942987 M=0.727538 FC=0.5 TT=4.33674e-09
+ KF=0 AF=1 )

* D5 model
.model 1N4148_2_D5 d (
+ IS=6.89131e-09 RS=0.636257 N=1.82683 EG=1.15805
+ XTI=0.518861 BV=80 IBV=0.0001 CJO=9.99628e-13
+ VJ=0.942987 M=0.727538 FC=0.5 TT=4.33674e-09
+ KF=0 AF=1 )

* D6 model
.model 1N4148_2_D6 d (
+ IS=6.89131e-09 RS=0.636257 N=1.82683 EG=1.15805
+ XTI=0.518861 BV=80 IBV=0.0001 CJO=9.99628e-13
+ VJ=0.942987 M=0.727538 FC=0.5 TT=4.33674e-09
+ KF=0 AF=1 )

* R1 model
.model VIRTUAL_RESISTANCE_R1 r( )

* R10 model
.model VIRTUAL_RESISTANCE_R10 r( )

* R2 model
.model VIRTUAL_RESISTANCE_R2 r( )

* R4 model
.model VIRTUAL_RESISTANCE_R4 r( )

* R6 model
.model VIRTUAL_RESISTANCE_R6 r( )

* R7 model
.model VIRTUAL_RESISTANCE_R7 r( )

* R9 model
.model VIRTUAL_RESISTANCE_R9 r( )

* --- Subcircuits ---

* R3 subcircuit
.subckt Potentiometer_R3 T1 T2 T3 PARAMS: res=10k posPercent=50
.PARAM relPos = limit(posPercent * 0.01, 0.0000001, 0.9999999)
r1 T1 T2 {{res}*relPos}
r2 T2 T3 {{res} - {res}*relPos}
.ends

* R5 subcircuit
.subckt Potentiometer_R5 T1 T2 T3 PARAMS: res=10k posPercent=50
.PARAM relPos = limit(posPercent * 0.01, 0.0000001, 0.9999999)
r1 T1 T2 {{res}*relPos}
r2 T2 T3 {{res} - {res}*relPos}
.ends

* R8 subcircuit
.subckt Potentiometer_R8 T1 T2 T3 PARAMS: res=10k posPercent=50
.PARAM relPos = limit(posPercent * 0.01, 0.0000001, 0.9999999)
r1 T1 T2 {{res}*relPos}
r2 T2 T3 {{res} - {res}*relPos}
.ends

* SCR_A1 subcircuit
.subckt SCR_IDEAL_SCR_A1 Anode Cathode Gate PARAMS: Vth=2.5 Ih=0 Vfscr=0 Ron=1m Roff=1meg
E3 a2 0 Value = { if(I(vIscr)<=Ih,5,0) }

vIscr Anode 10 dc 0

xU6 8 cathode DIODE_IDEAL params: Vf={Vfscr} Rd={Ron/2} Rdoff={Roff/2}
.subckt DIODE_IDEAL a k params: Vf=0 Rd=1m Rdoff=1meg
ad1 %vd(a k) %id(a k) diode1
.model diode1 pwl(x_array=[{Vf-1} {Vf} {Vf+1}] y_array=[{-1/Rdoff} 0 {1/Rd}] fraction=false input_domain=0.0)
.ends

xS1 10 8 a3 0 VSwitchS1
.subckt VSwitchS1 1 2 3 4
S1 1 2 3 4 vsw0
.model vsw0 vswitch ( Roff={Roff/2} Ron={Ron/2} Voff=0 Von=1 )
.ends

aU5 7 d_constsource_U5
.model d_constsource_U5 d_constsource(state=1)

aU4 [a1 dU4.B dU4.C] reset AND2__TIL__1
xU4.B a2 dU4.B TIL_RCV__NON__1
xU4.C a3 dU4.C TIL_RCV__NON__1
aU3 dU3.A a1 NOT__TIL__1

xU3.A gate dU3.A TIL_RCV__NON__1_Gate

aU2 dU2.S reset 7
+ U2_OPEN_SET U2_OPEN_RESET
+ dU2.Q U2_OPEN_notQ SR_LATCH__TIL__1

xU2.S gate dU2.S TIL_RCV__NON__1_Gate

xU2.Q dU2.Q a3 TIL_DRV__NON__1

.MODEL AND2__TIL__1 d_and ( rise_delay = 1n fall_delay = 1n)
.MODEL NOT__TIL__1 d_inverter (rise_delay = 1n fall_delay = 1n)
.SUBCKT TIL_DRV__NON__1 1 2
* TIL Driver Model 1 = D/A input, 2 = out
aDACin1 [1] [2] aDAC
.MODEL aDAC dac_bridge (out_low= 0 out_high = 5 out_undef = 0)
.ENDS

.SUBCKT TIL_RCV__NON__1_Gate 1 2
* TIL Receiver Model 1 = input, 2 = A/D out
aADCin1 [1] [2] ADC
.MODEL ADC adc_bridge (in_low= {Vth} in_high = {Vth})
.ENDS

.SUBCKT TIL_RCV__NON__1 1 2
* TIL Receiver Model 1 = input, 2 = A/D out
aADCin1 [1] [2] ADC
.MODEL ADC adc_bridge (in_low= 2.5 in_high = 2.5)
.ENDS

.MODEL SR_LATCH__TIL__1 d_srlatch (sr_delay = 1n enable_delay = 1n
+ set_delay = 1n reset_delay= 1n
+ ic = 0 rise_delay = 1n fall_delay = 1n)

.ends

* SCR_A2 subcircuit
.subckt SCR_IDEAL_SCR_A2 Anode Cathode Gate PARAMS: Vth=2.5 Ih=0 Vfscr=0 Ron=1m Roff=1meg
E3 a2 0 Value = { if(I(vIscr)<=Ih,5,0) }

vIscr Anode 10 dc 0

xU6 8 cathode DIODE_IDEAL params: Vf={Vfscr} Rd={Ron/2} Rdoff={Roff/2}
.subckt DIODE_IDEAL a k params: Vf=0 Rd=1m Rdoff=1meg
ad1 %vd(a k) %id(a k) diode1
.model diode1 pwl(x_array=[{Vf-1} {Vf} {Vf+1}] y_array=[{-1/Rdoff} 0 {1/Rd}] fraction=false input_domain=0.0)
.ends

xS1 10 8 a3 0 VSwitchS1
.subckt VSwitchS1 1 2 3 4
S1 1 2 3 4 vsw0
.model vsw0 vswitch ( Roff={Roff/2} Ron={Ron/2} Voff=0 Von=1 )
.ends

aU5 7 d_constsource_U5
.model d_constsource_U5 d_constsource(state=1)

aU4 [a1 dU4.B dU4.C] reset AND2__TIL__1
xU4.B a2 dU4.B TIL_RCV__NON__1
xU4.C a3 dU4.C TIL_RCV__NON__1
aU3 dU3.A a1 NOT__TIL__1

xU3.A gate dU3.A TIL_RCV__NON__1_Gate

aU2 dU2.S reset 7
+ U2_OPEN_SET U2_OPEN_RESET
+ dU2.Q U2_OPEN_notQ SR_LATCH__TIL__1

xU2.S gate dU2.S TIL_RCV__NON__1_Gate

xU2.Q dU2.Q a3 TIL_DRV__NON__1

.MODEL AND2__TIL__1 d_and ( rise_delay = 1n fall_delay = 1n)
.MODEL NOT__TIL__1 d_inverter (rise_delay = 1n fall_delay = 1n)
.SUBCKT TIL_DRV__NON__1 1 2
* TIL Driver Model 1 = D/A input, 2 = out
aDACin1 [1] [2] aDAC
.MODEL aDAC dac_bridge (out_low= 0 out_high = 5 out_undef = 0)
.ENDS

.SUBCKT TIL_RCV__NON__1_Gate 1 2
* TIL Receiver Model 1 = input, 2 = A/D out
aADCin1 [1] [2] ADC
.MODEL ADC adc_bridge (in_low= {Vth} in_high = {Vth})
.ENDS

.SUBCKT TIL_RCV__NON__1 1 2
* TIL Receiver Model 1 = input, 2 = A/D out
aADCin1 [1] [2] ADC
.MODEL ADC adc_bridge (in_low= 2.5 in_high = 2.5)
.ENDS

.MODEL SR_LATCH__TIL__1 d_srlatch (sr_delay = 1n enable_delay = 1n
+ set_delay = 1n reset_delay= 1n
+ ic = 0 rise_delay = 1n fall_delay = 1n)

.ends

* SCR_A3 subcircuit
.subckt SCR_IDEAL_SCR_A3 Anode Cathode Gate PARAMS: Vth=2.5 Ih=0 Vfscr=0 Ron=1m Roff=1meg
E3 a2 0 Value = { if(I(vIscr)<=Ih,5,0) }

vIscr Anode 10 dc 0

xU6 8 cathode DIODE_IDEAL params: Vf={Vfscr} Rd={Ron/2} Rdoff={Roff/2}
.subckt DIODE_IDEAL a k params: Vf=0 Rd=1m Rdoff=1meg
ad1 %vd(a k) %id(a k) diode1
.model diode1 pwl(x_array=[{Vf-1} {Vf} {Vf+1}] y_array=[{-1/Rdoff} 0 {1/Rd}] fraction=false input_domain=0.0)
.ends

xS1 10 8 a3 0 VSwitchS1
.subckt VSwitchS1 1 2 3 4
S1 1 2 3 4 vsw0
.model vsw0 vswitch ( Roff={Roff/2} Ron={Ron/2} Voff=0 Von=1 )
.ends

aU5 7 d_constsource_U5
.model d_constsource_U5 d_constsource(state=1)

aU4 [a1 dU4.B dU4.C] reset AND2__TIL__1
xU4.B a2 dU4.B TIL_RCV__NON__1
xU4.C a3 dU4.C TIL_RCV__NON__1
aU3 dU3.A a1 NOT__TIL__1

xU3.A gate dU3.A TIL_RCV__NON__1_Gate

aU2 dU2.S reset 7
+ U2_OPEN_SET U2_OPEN_RESET
+ dU2.Q U2_OPEN_notQ SR_LATCH__TIL__1

xU2.S gate dU2.S TIL_RCV__NON__1_Gate

xU2.Q dU2.Q a3 TIL_DRV__NON__1

.MODEL AND2__TIL__1 d_and ( rise_delay = 1n fall_delay = 1n)
.MODEL NOT__TIL__1 d_inverter (rise_delay = 1n fall_delay = 1n)
.SUBCKT TIL_DRV__NON__1 1 2
* TIL Driver Model 1 = D/A input, 2 = out
aDACin1 [1] [2] aDAC
.MODEL aDAC dac_bridge (out_low= 0 out_high = 5 out_undef = 0)
.ENDS

.SUBCKT TIL_RCV__NON__1_Gate 1 2
* TIL Receiver Model 1 = input, 2 = A/D out
aADCin1 [1] [2] ADC
.MODEL ADC adc_bridge (in_low= {Vth} in_high = {Vth})
.ENDS

.SUBCKT TIL_RCV__NON__1 1 2
* TIL Receiver Model 1 = input, 2 = A/D out
aADCin1 [1] [2] ADC
.MODEL ADC adc_bridge (in_low= 2.5 in_high = 2.5)
.ENDS

.MODEL SR_LATCH__TIL__1 d_srlatch (sr_delay = 1n enable_delay = 1n
+ set_delay = 1n reset_delay= 1n
+ ic = 0 rise_delay = 1n fall_delay = 1n)

.ends

* V1 subcircuit
.subckt 3PHDELTA_V1 1 2 3 PARAMS: vrms=120 freq=60 td=0 damp=0
.FUNC RMS_TO_PEAK(in) { in*1.414323562 }
V1 1 2 ac 1 0 sin(0 RMS_TO_PEAK({vrms}) {freq} {td} {damp} 0)
V2 2 3 ac 1 120 sin(0 RMS_TO_PEAK({vrms}) {freq} {td} {damp} 120)
.ends

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Item

Document

Section

Only one section is available for multisection components.

Type

Rise time

Time it takes for signal to transition from low to high.

With non-zero rise time, the signal converts to an analog signal from a digital signal.

Fall time

Time it takes for signal to transition from high to low.

With non-zero fall time, the signal converts to an analog signal from a digital signal.

Use document settings

Use logic levels settings from Document tab.

Threshold voltage levels.

Threshold voltage values used in the logic evaluation. See Digital Simulation for more information.

Output low

Output low voltage.

Maximum output voltage level to produce a low signal.

Input low threshold

Input low threshold voltage.

Maximum input voltage level for the signal to be considered low.

Input high threshold

Input high threshold voltage.

Minimum input voltage level for the signal to be considered high.

Output high

Output high voltage.

Minimum output voltage level to produce a high signal.

Type Probe

Select desired function.

Function

Use document settings

Use logic levels settings from Document tab.

Threshold voltage levels.

Threshold voltage values used in the logic evaluation. See Digital Simulation for more information.

Output low

Output low voltage.

Maximum output voltage level to produce a low signal.

Input low threshold

Input low threshold voltage.

Maximum input voltage level for the signal to be considered low.

Input high threshold

Input high threshold voltage.

Minimum input voltage level for the signal to be considered high.

Output high

Output high voltage.

Minimum output voltage level to produce a high signal.

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Source type

Application used to generate the Source data.

Data type

Type of simulation data in Source.

File size

Size of the referenced file. Total file size for all data plotters cannot exceed 100 MB.

Selected simulation type does not match uploaded simulation data

Data streaming is only available in interactive simulation

Instantaneous

Displays instantaneous measurements on probe during interactive simulation.

Periodic

Displays periodic measurements on probe during Interactive simulation.

Bias point(s)

Displays bias points on probe for DC Op simulation.

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Name single phase half wave controlled rectifier(from 0 to 90 degree)

Type Schematic

The simulation to run. See Simulation types for more information.

Name

Title of graph. Edit as desired.

End time

Time at which the simulation stops. Does not include pauses. Simulation does not occur in real time.

Start simulation

RELTOL

Relative error tolerance. A simulation wide accuracy control used to establish convergence.

VNTOL

Absolute voltage error tolerance. Defines the minimum value for voltage where it may still be considered accurate.

ABSTOL

Absolute current error tolerance. Defines the minimum value for current where it may still be considered accurate.

ITL1

DC iteration limit. Number of iterative passes done on DC circuit equations in attempt to reach convergence in simulation.

ITL4

Upper iteration limit. Number of iterative passes done per time point, on Transient circuit equations in attempt to reach convergence in simulation.

Integration method. The numerical integration method used in transient analysis.

Temp

℃

Operating temperature. The temperature at which the entire circuit will be simulated.

Insert shunt resistance

Inserts a resistance of RSHUNT from every analog node to ground. Will aid in convergence, but alter the behavior of the circuit.

RSHUNT

Shunt resistance. This eliminates singular matrix errors that result from a lack of a DC path to ground.

Reset to default

Threshold voltage levels.

Threshold voltage values used in the logic evaluation. See Digital Simulation for more information.

Output low

Output low voltage.

Maximum output voltage level to produce a low signal.

Input low threshold

Input low threshold voltage.

Maximum input voltage level for the signal to be considered low.

Input high threshold

Input high threshold voltage.

Minimum input voltage level for the signal to be considered high.

Output high

Output high voltage.

Minimum output voltage level to produce a high signal.

Width

Sheet width in grid squares.

Height

Sheet height in grid squares.

Grid

Toggles grid display.

Net Labels

Toggles all net labels.

Component Labels

Toggles all component labels.

single phase half wave controlled rectifier(from 0 to 90 degree)