Initializing Multisim Live ...

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U18ABCDU1U2U3U4U5U6U71234U976U10U11U128U13U85U14U15U16U17U19U2091011121314151617181920212223DG524

ID:

ID:

x10
x0.1
Sheet:1
V
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Digital
10
Digital Constant
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1234567891011121314
BCD to 7-Segment Decoders
BCD to 7-Segment Decoders
1234567891011121314
74LS47N
74LS48N
12345678
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12345678
74LS93N
74LS193N
1234567
Mux/Demux
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1234567
74LS139D
12345
Adders
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12345
74LS183D
Disable streaming
Details
Netlist
Errors
SPICE
SPICE Netlist

This is a text-based representation of the circuit.
The * symbol indicates a comment.
The + symbol indicates a continuation from the previous line.
Probes do not appear in netlists.

** 7-Segment Display indicator **
*
* Multisim Live SPICE netlist
*
*

* --- Circuit Topology ---

* Component: A
aA 1 Digital_Source_A

* Component: B
aB 2 Digital_Source_B

* Component: C
aC 3 Digital_Source_C

* Component: D
aD 4 Digital_Source_D

* Component: DG5
aDG5 bridgeDG5!OUT Digital_Source_DG5

xbridgeDG5!OUT bridgeDG5!OUT 24 REAL_CUSTOM_DAC PARAMS: lowV=0 maxLowV=0.8 unknownV=1 minHighV=2 highV=3.3 riseT=0 fallT=0

* Component: U1
aU1 [7 6 5] 9 Digital_AND3_U1

* Component: U10
aU10 [7 2] 15 Digital_AND2_U10

* Component: U11
aU11 [2 3 4] 10 Digital_AND3_U11

* Component: U12
aU12 [6 3 8] bridgeU12!Y Digital_AND3_U12

xbridgeU12!Y bridgeU12!Y 14 REAL_CUSTOM_DAC PARAMS: lowV=0 maxLowV=0.8 unknownV=1 minHighV=2 highV=3.3 riseT=0 fallT=0

* Component: U13
aU13 [3 4] 16 Digital_XOR2_U13

* Component: U14
aU14 [12 13 bridgeU14!C] bridgeU14!Y Digital_OR3_U14

xbridgeU14!C bridgeU14!C 14 REAL_CUSTOM_ADC PARAMS: lowV=0 maxLowV=0.8 unknownV=1 minHighV=2 highV=3.3 riseT=0 fallT=0

xbridgeU14!Y bridgeU14!Y 22 REAL_CUSTOM_DAC PARAMS: lowV=0 maxLowV=0.8 unknownV=1 minHighV=2 highV=3.3 riseT=0 fallT=0

* Component: U15
aU15 [10 9] bridgeU15!Y Digital_OR2_U15

xbridgeU15!Y bridgeU15!Y 23 REAL_CUSTOM_DAC PARAMS: lowV=0 maxLowV=0.8 unknownV=1 minHighV=2 highV=3.3 riseT=0 fallT=0

* Component: U16
aU16 [4 15] bridgeU16!Y Digital_OR2_U16

xbridgeU16!Y bridgeU16!Y 21 REAL_CUSTOM_DAC PARAMS: lowV=0 maxLowV=0.8 unknownV=1 minHighV=2 highV=3.3 riseT=0 fallT=0

* Component: U17
aU17 [bridgeU17!A 10] bridgeU17!Y Digital_OR2_U17

xbridgeU17!A bridgeU17!A 11 REAL_CUSTOM_ADC PARAMS: lowV=0 maxLowV=0.8 unknownV=1 minHighV=2 highV=3.3 riseT=0 fallT=0

xbridgeU17!Y bridgeU17!Y 20 REAL_CUSTOM_DAC PARAMS: lowV=0 maxLowV=0.8 unknownV=1 minHighV=2 highV=3.3 riseT=0 fallT=0

* Component: U18
xU18 11 19 14 20 21 22 23 24 7_SEGMENT_CA_U18

* Component: U19
aU19 [2 16] bridgeU19!Y Digital_AND2_U19

xbridgeU19!Y bridgeU19!Y 19 REAL_CUSTOM_DAC PARAMS: lowV=0 maxLowV=0.8 unknownV=1 minHighV=2 highV=3.3 riseT=0 fallT=0

* Component: U2
aU2 [5 6 4] 13 Digital_AND3_U2

* Component: U20
aU20 [18 17] bridgeU20!Y Digital_OR2_U20

xbridgeU20!Y bridgeU20!Y 11 REAL_CUSTOM_DAC PARAMS: lowV=0 maxLowV=0.8 unknownV=1 minHighV=2 highV=3.3 riseT=0 fallT=0

* Component: U3
aU3 [3 4] 12 Digital_AND2_U3

* Component: U4
aU4 1 5 Digital_Inverter_U4

* Component: U5
aU5 2 6 Digital_Inverter_U5

* Component: U6
aU6 3 7 Digital_Inverter_U6

* Component: U7
aU7 4 8 Digital_Inverter_U7

* Component: U8
aU8 [5 6 7 4] 18 Digital_AND4_U8

* Component: U9
aU9 [2 7 8] 17 Digital_AND3_U9


* --- Circuit Models ---

* A model
.model Digital_Source_A d_constsource(State=0)

* B model
.model Digital_Source_B d_constsource(State=0)

* C model
.model Digital_Source_C d_constsource(State=0)

* D model
.model Digital_Source_D d_constsource(State=1)

* DG5 model
.model Digital_Source_DG5 d_constsource(State=1)

* U1 model
.model Digital_AND3_U1 d_and (rise_delay=1e-9 fall_delay=1e-9)

* U10 model
.model Digital_AND2_U10 d_and (rise_delay=1e-9 fall_delay=1e-9)

* U11 model
.model Digital_AND3_U11 d_and (rise_delay=1e-9 fall_delay=1e-9)

* U12 model
.model Digital_AND3_U12 d_and (rise_delay=1e-9 fall_delay=1e-9)

* U13 model
.model Digital_XOR2_U13 d_xor (rise_delay=1e-9 fall_delay=1e-9)

* U14 model
.model Digital_OR3_U14 d_or (rise_delay=1e-9 fall_delay=1e-9)

* U15 model
.model Digital_OR2_U15 d_or (rise_delay=1e-9 fall_delay=1e-9)

* U16 model
.model Digital_OR2_U16 d_or (rise_delay=1e-9 fall_delay=1e-9)

* U17 model
.model Digital_OR2_U17 d_or (rise_delay=1e-9 fall_delay=1e-9)

* U19 model
.model Digital_AND2_U19 d_and (rise_delay=1e-9 fall_delay=1e-9)

* U2 model
.model Digital_AND3_U2 d_and (rise_delay=1e-9 fall_delay=1e-9)

* U20 model
.model Digital_OR2_U20 d_or (rise_delay=1e-9 fall_delay=1e-9)

* U3 model
.model Digital_AND2_U3 d_and (rise_delay=1e-9 fall_delay=1e-9)

* U4 model
.model Digital_Inverter_U4 d_inverter (rise_delay=1e-9 fall_delay=1e-9)

* U5 model
.model Digital_Inverter_U5 d_inverter (rise_delay=1e-9 fall_delay=1e-9)

* U6 model
.model Digital_Inverter_U6 d_inverter (rise_delay=1e-9 fall_delay=1e-9)

* U7 model
.model Digital_Inverter_U7 d_inverter (rise_delay=1e-9 fall_delay=1e-9)

* U8 model
.model Digital_AND4_U8 d_and (rise_delay=1e-9 fall_delay=1e-9)

* U9 model
.model Digital_AND3_U9 d_and (rise_delay=1e-9 fall_delay=1e-9)


* --- Subcircuits ---

* U18 subcircuit
.subckt 7_SEGMENT_CA_U18 K1 K2 K3 K4 K5 K6 K7 A

dd1 A 0vNode1 ledDiodeModel
Vsense1 0vNode1 K1 DC 0
* Interactive sense node
b1 lit1 0 v = { if (i(Vsense1) < 0, 0, if( i(Vsense1) > 0.02, 1, { i(Vsense1) / 0.02 })) }

dd2 A 0vNode2 ledDiodeModel
Vsense2 0vNode2 K2 DC 0
* Interactive sense node
b2 lit2 0 v = { if (i(Vsense2) < 0, 0, if( i(Vsense2) > 0.02, 1, { i(Vsense2) / 0.02 })) }

dd3 A 0vNode3 ledDiodeModel
Vsense3 0vNode3 K3 DC 0
* Interactive sense node
b3 lit3 0 v = { if (i(Vsense3) < 0, 0, if( i(Vsense3) > 0.02, 1, { i(Vsense3) / 0.02 })) }

dd4 A 0vNode4 ledDiodeModel
Vsense4 0vNode4 K4 DC 0
* Interactive sense node
b4 lit4 0 v = { if (i(Vsense4) < 0, 0, if( i(Vsense4) > 0.02, 1, { i(Vsense4) / 0.02 })) }

dd5 A 0vNode5 ledDiodeModel
Vsense5 0vNode5 K5 DC 0
* Interactive sense node
b5 lit5 0 v = { if (i(Vsense5) < 0, 0, if( i(Vsense5) > 0.02, 1, { i(Vsense5) / 0.02 })) }

dd6 A 0vNode6 ledDiodeModel
Vsense6 0vNode6 K6 DC 0
* Interactive sense node
b6 lit6 0 v = { if (i(Vsense6) < 0, 0, if( i(Vsense6) > 0.02, 1, { i(Vsense6) / 0.02 })) }

dd7 A 0vNode7 ledDiodeModel
Vsense7 0vNode7 K7 DC 0
* Interactive sense node
b7 lit7 0 v = { if (i(Vsense7) < 0, 0, if( i(Vsense7) > 0.02, 1, { i(Vsense7) / 0.02 })) }

.model ledDiodeModel D( IS=1e-14 N=1 RS=0 IBV=1e-10 BV=1e+30 CJO=0 M=0.5 VJ=1 )
.ends


* --- Pin bridge models

.SUBCKT REAL_CUSTOM_DAC 1 2 PARAMS: lowV=0 maxLowV=0.8 unknownV=1.0 minHighV=2.0 highV=5.0 riseT=0 fallT=0
* Ideal Driver Model 1 = A/D out, 2 = input
aDACin1 [1] [2] aDAC
.MODEL aDAC dac_bridge (out_low = {lowV} out_high = {highV} out_undef = {unknownV} t_rise = {max(riseT,1e-9)} t_fall = {max(fallT,1e-9)})
.ENDS

.SUBCKT REAL_CUSTOM_ADC 1 2 PARAMS: lowV=0 maxLowV=0.8 unknownV=1.0 minHighV=2.0 highV=5.0 riseT=0 fallT=0
* Ideal Receiver Model 1 = input, 2 = A/D out
aADCin1 [2] [1] ADC
.MODEL ADC adc_bridge (in_low = {maxLowV} in_high = {minHighV})
.ENDS
Errors and Warnings

Any error, warning or information messages appear below.

Item
Document
No items selected.
7-Segment Display indicator
Schematic

The simulation to run. See Simulation types for more information.

Name

Title of graph. Edit as desired.

End time

s

Time at which the simulation stops. Does not include pauses. Simulation does not occur in real time.

Start simulation

Mode

Threshold voltage levels.

Threshold voltage values used in the logic evaluation. See Digital Simulation for more information.

Output low

V

Output low voltage.

Maximum output voltage level to produce a low signal.

Input low threshold

V

Input low threshold voltage.

Maximum input voltage level for the signal to be considered low.

Input high threshold

V

Input high threshold voltage.

Minimum input voltage level for the signal to be considered high.

Output high

V

Output high voltage.

Minimum output voltage level to produce a high signal.

Width

Sheet width in grid squares.

Height

Sheet height in grid squares.

Grid

Toggles grid display.

Net Labels

Toggles all net labels.

Component Labels

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