*4.1.2-DOB_STATE_MACHINE-Diego Ayala

Waiting for data

Signal	Value
Signal	Value

Cursor 1	Cursor 2	∆X	1/∆X	∆Y	∆Y (Phase)

Out of date
V	—
V	—
V_PP	—
V_RMS	—
V_AV	—
f_V	—
I	—
I	—
I_PP	—
I_RMS	—
I_AV	—
f_I	—
D	—

Out of date
V	—
V	—
V_PP	—
V_RMS	—
V_AV	—
f_V	—
I	—
I	—
I_PP	—
I_RMS	—
I_AV	—
f_I	—
D	—

Out of date
V	—
V	—
V_PP	—
V_RMS	—
V_AV	—
f_V	—
I	—
I	—
I_PP	—
I_RMS	—
I_AV	—
f_I	—
D	—

Out of date
V	—
V	—
V_PP	—
V_RMS	—
V_AV	—
f_V	—
I	—
I	—
I_PP	—
I_RMS	—
I_AV	—
f_I	—
D	—

Out of date
V	—
V	—
V_PP	—
V_RMS	—
V_AV	—
f_V	—
I	—
I	—
I_PP	—
I_RMS	—
I_AV	—
f_I	—
D	—

Out of date
V	—
V	—
V_PP	—
V_RMS	—
V_AV	—
f_V	—
I	—
I	—
I_PP	—
I_RMS	—
I_AV	—
f_I	—
D	—

Out of date
V	—
V	—
V_PP	—
V_RMS	—
V_AV	—
f_V	—
I	—
I	—
I_PP	—
I_RMS	—
I_AV	—
f_I	—
D	—

Out of date
V	—
V	—
V_PP	—
V_RMS	—
V_AV	—
f_V	—
I	—
I	—
I_PP	—
I_RMS	—
I_AV	—
f_I	—
D	—

Out of date
V	—
V	—
V_PP	—
V_RMS	—
V_AV	—
f_V	—
I	—
I	—
I_PP	—
I_RMS	—
I_AV	—
f_I	—
D	—

ID:

x10

x0.1

Sheet:1

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SPICE

SPICE Netlist

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** 4.1.2-DOB_STATE_MACHINE-Diego Ayala **
*
* Multisim Live SPICE netlist
*
*

* --- Circuit Topology ---

* Component: A
xA 23 bridgeA!CLK 1 1 QA NOTQA Digital_DFlipFlop_A PARAMS: Negative_Edge_Clock=0 Negative_SET_RESET=1 Rise_delay=1e-9 Fall_delay=1e-9 Clk_delay=1e-9 Set_delay=1e-9 Reset_delay=1e-9 Ic=0

xbridgeA!CLK bridgeA!CLK 28 REAL_CUSTOM_ADC PARAMS: lowV=0 maxLowV=0.8 unknownV=1 minHighV=2 highV=5 riseT=0 fallT=0

* Component: B
xB 33 bridgeB!CLK 1 1 QB NOTQB Digital_DFlipFlop_B PARAMS: Negative_Edge_Clock=0 Negative_SET_RESET=1 Rise_delay=1e-9 Fall_delay=1e-9 Clk_delay=1e-9 Set_delay=1e-9 Reset_delay=1e-9 Ic=0

xbridgeB!CLK bridgeB!CLK 28 REAL_CUSTOM_ADC PARAMS: lowV=0 maxLowV=0.8 unknownV=1 minHighV=2 highV=5 riseT=0 fallT=0

* Component: C
xC 37 bridgeC!CLK 1 1 QC NOTQC Digital_DFlipFlop_C PARAMS: Negative_Edge_Clock=0 Negative_SET_RESET=1 Rise_delay=1e-9 Fall_delay=1e-9 Clk_delay=1e-9 Set_delay=1e-9 Reset_delay=1e-9 Ic=0

xbridgeC!CLK bridgeC!CLK 28 REAL_CUSTOM_ADC PARAMS: lowV=0 maxLowV=0.8 unknownV=1 minHighV=2 highV=5 riseT=0 fallT=0

* Component: C0_BLUE
aC0_BLUE [NOTQA QC] 40 Digital_AND2_C0_BLUE

* Component: C0_GREEN
aC0_GREEN [NOTQA NOTQB] 38 Digital_AND2_C0_GREEN

* Component: C1_BLUE
aC1_BLUE [QA NOTQB NOTQC] 41 Digital_AND3_C1_BLUE

* Component: C1_GREEN
aC1_GREEN [QA QB QC] 42 Digital_AND3_C1_GREEN

* Component: C2
aC2 [QA QB QC] 44 Digital_AND3_C2

* Component: CD_BLUE
aCD_BLUE [QA NOTQB QC] 48 Digital_AND3_CD_BLUE

* Component: CD_GREEN
aCD_GREEN [NOTQA QB NOTQC] 47 Digital_AND3_CD_GREEN

* Component: DA
aDA [24 27 31 32] 23 Digital_OR4_DA

* Component: DA_BLUE
aDA_BLUE [NOTQA QB QC bridgeDA_BLUE!D] 24 Digital_AND4_DA_BLUE

xbridgeDA_BLUE!D bridgeDA_BLUE!D 30 REAL_CUSTOM_ADC PARAMS: lowV=0 maxLowV=0.8 unknownV=1 minHighV=2 highV=5 riseT=0 fallT=0

* Component: DA_BROWN
aDA_BROWN [QA NOTQB] 31 Digital_AND2_DA_BROWN

* Component: DA_GREEN
aDA_GREEN [QA NOTQC] 27 Digital_AND2_DA_GREEN

* Component: DA_YELLOW
aDA_YELLOW [QA 22] 32 Digital_AND2_DA_YELLOW

* Component: DB_BLUE
aDB_BLUE [QB NOTQC] 34 Digital_AND2_DB_BLUE

* Component: DB_BROWN
aDB_BROWN [NOTQB QC bridgeDB_BROWN!C] 36 Digital_AND3_DB_BROWN

xbridgeDB_BROWN!C bridgeDB_BROWN!C 30 REAL_CUSTOM_ADC PARAMS: lowV=0 maxLowV=0.8 unknownV=1 minHighV=2 highV=5 riseT=0 fallT=0

* Component: DB_GREEN
aDB_GREEN [QB 22] 35 Digital_AND2_DB_GREEN

* Component: DC
aDC [QC bridgeDC!B] 37 Digital_XOR2_DC

xbridgeDC!B bridgeDC!B 30 REAL_CUSTOM_ADC PARAMS: lowV=0 maxLowV=0.8 unknownV=1 minHighV=2 highV=5 riseT=0 fallT=0

* Component: DG1
aDG1 bridgeDG1!OUT Digital_Source_DG1

xbridgeDG1!OUT bridgeDG1!OUT 29 REAL_CUSTOM_DAC PARAMS: lowV=0 maxLowV=0.8 unknownV=1 minHighV=2 highV=5 riseT=0 fallT=0

* Component: DG2
aDG2 1 Digital_Source_DG2

* Component: DG3
aDG3 25 Digital_Source_DG3

* Component: DG4
aDG4 bridgeDG4!OUT Digital_Source_DG4

xbridgeDG4!OUT bridgeDG4!OUT 46 REAL_CUSTOM_DAC PARAMS: lowV=0 maxLowV=0.8 unknownV=1 minHighV=2 highV=5 riseT=0 fallT=0

* Component: EN
xEN 0 30 29 SPDT_Switch_EN Params: Ron=0.0001 Roff=100000000 State=1

* Component: RA
rRA 4 16 220 VIRTUAL_RESISTANCE_RA

* Component: RB
rRB 5 15 220 VIRTUAL_RESISTANCE_RB

* Component: RC
rRC 6 14 220 VIRTUAL_RESISTANCE_RC

* Component: RD
rRD 7 13 220 VIRTUAL_RESISTANCE_RD

* Component: RE
rRE 8 12 220 VIRTUAL_RESISTANCE_RE

* Component: RF
rRF 9 11 220 VIRTUAL_RESISTANCE_RF

* Component: RG
rRG 45 10 220 VIRTUAL_RESISTANCE_RG

* Component: U1
xU1 39 43 44 bridgeU1!D 25 25 25 2 18 19 20 17 3 21 74LS47_U1 PARAMS: Rise_delay=1e-7 Fall_delay=1e-7

xbridgeU1!D bridgeU1!D 0 REAL_CUSTOM_ADC PARAMS: lowV=0 maxLowV=0.8 unknownV=1 minHighV=2 highV=5 riseT=0 fallT=0

* Component: U10
aU10 [18 26] bridgeU10!Y Digital_XOR2_U10

xbridgeU10!Y bridgeU10!Y 13 REAL_CUSTOM_DAC PARAMS: lowV=0 maxLowV=0.8 unknownV=1 minHighV=2 highV=5 riseT=0 fallT=0

* Component: U13
aU13 [17 26] bridgeU13!Y Digital_XOR2_U13

xbridgeU13!Y bridgeU13!Y 14 REAL_CUSTOM_DAC PARAMS: lowV=0 maxLowV=0.8 unknownV=1 minHighV=2 highV=5 riseT=0 fallT=0

* Component: U15
aU15 [3 26] bridgeU15!Y Digital_XOR2_U15

xbridgeU15!Y bridgeU15!Y 15 REAL_CUSTOM_DAC PARAMS: lowV=0 maxLowV=0.8 unknownV=1 minHighV=2 highV=5 riseT=0 fallT=0

* Component: U16
aU16 [2 26] bridgeU16!Y Digital_XOR2_U16

xbridgeU16!Y bridgeU16!Y 16 REAL_CUSTOM_DAC PARAMS: lowV=0 maxLowV=0.8 unknownV=1 minHighV=2 highV=5 riseT=0 fallT=0

* Component: U18
xU18 4 5 6 7 8 9 45 46 7_SEGMENT_CA_U18

* Component: U2
aU2 bridgeU2!A 22 Digital_Inverter_U2

xbridgeU2!A bridgeU2!A 30 REAL_CUSTOM_ADC PARAMS: lowV=0 maxLowV=0.8 unknownV=1 minHighV=2 highV=5 riseT=0 fallT=0

* Component: U3
aU3 [34 35 36] 33 Digital_OR3_U3

* Component: U4
aU4 [38 40] 39 Digital_OR2_U4

* Component: U5
aU5 [41 42] 43 Digital_OR2_U5

* Component: U6
aU6 [21 26] bridgeU6!Y Digital_XOR2_U6

xbridgeU6!Y bridgeU6!Y 10 REAL_CUSTOM_DAC PARAMS: lowV=0 maxLowV=0.8 unknownV=1 minHighV=2 highV=5 riseT=0 fallT=0

* Component: U7
aU7 [47 48] 26 Digital_OR2_U7

* Component: U8
aU8 [20 26] bridgeU8!Y Digital_XOR2_U8

xbridgeU8!Y bridgeU8!Y 11 REAL_CUSTOM_DAC PARAMS: lowV=0 maxLowV=0.8 unknownV=1 minHighV=2 highV=5 riseT=0 fallT=0

* Component: U9
aU9 [19 26] bridgeU9!Y Digital_XOR2_U9

xbridgeU9!Y bridgeU9!Y 12 REAL_CUSTOM_DAC PARAMS: lowV=0 maxLowV=0.8 unknownV=1 minHighV=2 highV=5 riseT=0 fallT=0

* Component: V1
vV1 28 0
+ pulse( 0 5 0 1e-9 1e-9
+ { 50 * 0.01 / 40 }
+ { 1/40 } )

* --- Circuit Models ---

* C0_BLUE model
.model Digital_AND2_C0_BLUE d_and (rise_delay=1e-9 fall_delay=1e-9)

* C0_GREEN model
.model Digital_AND2_C0_GREEN d_and (rise_delay=1e-9 fall_delay=1e-9)

* C1_BLUE model
.model Digital_AND3_C1_BLUE d_and (rise_delay=1e-9 fall_delay=1e-9)

* C1_GREEN model
.model Digital_AND3_C1_GREEN d_and (rise_delay=1e-9 fall_delay=1e-9)

* C2 model
.model Digital_AND3_C2 d_and (rise_delay=1e-9 fall_delay=1e-9)

* CD_BLUE model
.model Digital_AND3_CD_BLUE d_and (rise_delay=1e-9 fall_delay=1e-9)

* CD_GREEN model
.model Digital_AND3_CD_GREEN d_and (rise_delay=1e-9 fall_delay=1e-9)

* DA model
.model Digital_OR4_DA d_or (rise_delay=1e-9 fall_delay=1e-9)

* DA_BLUE model
.model Digital_AND4_DA_BLUE d_and (rise_delay=1e-9 fall_delay=1e-9)

* DA_BROWN model
.model Digital_AND2_DA_BROWN d_and (rise_delay=1e-9 fall_delay=1e-9)

* DA_GREEN model
.model Digital_AND2_DA_GREEN d_and (rise_delay=1e-9 fall_delay=1e-9)

* DA_YELLOW model
.model Digital_AND2_DA_YELLOW d_and (rise_delay=1e-9 fall_delay=1e-9)

* DB_BLUE model
.model Digital_AND2_DB_BLUE d_and (rise_delay=1e-9 fall_delay=1e-9)

* DB_BROWN model
.model Digital_AND3_DB_BROWN d_and (rise_delay=1e-9 fall_delay=1e-9)

* DB_GREEN model
.model Digital_AND2_DB_GREEN d_and (rise_delay=1e-9 fall_delay=1e-9)

* DC model
.model Digital_XOR2_DC d_xor (rise_delay=1e-9 fall_delay=1e-9)

* DG1 model
.model Digital_Source_DG1 d_constsource(State=1)

* DG2 model
.model Digital_Source_DG2 d_constsource(State=1)

* DG3 model
.model Digital_Source_DG3 d_constsource(State=1)

* DG4 model
.model Digital_Source_DG4 d_constsource(State=1)

* RA model
.model VIRTUAL_RESISTANCE_RA r( )

* RB model
.model VIRTUAL_RESISTANCE_RB r( )

* RC model
.model VIRTUAL_RESISTANCE_RC r( )

* RD model
.model VIRTUAL_RESISTANCE_RD r( )

* RE model
.model VIRTUAL_RESISTANCE_RE r( )

* RF model
.model VIRTUAL_RESISTANCE_RF r( )

* RG model
.model VIRTUAL_RESISTANCE_RG r( )

* U10 model
.model Digital_XOR2_U10 d_xor (rise_delay=1e-9 fall_delay=1e-9)

* U13 model
.model Digital_XOR2_U13 d_xor (rise_delay=1e-9 fall_delay=1e-9)

* U15 model
.model Digital_XOR2_U15 d_xor (rise_delay=1e-9 fall_delay=1e-9)

* U16 model
.model Digital_XOR2_U16 d_xor (rise_delay=1e-9 fall_delay=1e-9)

* U2 model
.model Digital_Inverter_U2 d_inverter (rise_delay=1e-9 fall_delay=1e-9)

* U3 model
.model Digital_OR3_U3 d_or (rise_delay=1e-9 fall_delay=1e-9)

* U4 model
.model Digital_OR2_U4 d_or (rise_delay=1e-9 fall_delay=1e-9)

* U5 model
.model Digital_OR2_U5 d_or (rise_delay=1e-9 fall_delay=1e-9)

* U6 model
.model Digital_XOR2_U6 d_xor (rise_delay=1e-9 fall_delay=1e-9)

* U7 model
.model Digital_OR2_U7 d_or (rise_delay=1e-9 fall_delay=1e-9)

* U8 model
.model Digital_XOR2_U8 d_xor (rise_delay=1e-9 fall_delay=1e-9)

* U9 model
.model Digital_XOR2_U9 d_xor (rise_delay=1e-9 fall_delay=1e-9)

* --- Subcircuits ---

* A subcircuit
.subckt Digital_DFlipFlop_A 1 2 3 4 5 6 PARAMS: Negative_Edge_Clock=0 Negative_SET_RESET=0 Clk_delay=1n Set_delay=1n Reset_delay=1n Ic=0 Rise_delay=1n Fall_delay=1n
*PIN MAPPING: D Q ~Q RESET CLK SET
* 1 5 6 4 2 3
*MODELS USED
aDG1 neg_SR Digital_SourceSR
aDG2 neg_clk Digital_SourceCLK
Axor1 [3 neg_SR] set xor
Axor2 [2 neg_clk] clk xor
Axor3 [4 neg_SR] reset xor
Ajkff 1 clk set reset 5 6 D_FF

.model Digital_SourceCLK d_constsource(State={Negative_Edge_Clock})
.model Digital_SourceSR d_constsource(State={Negative_SET_RESET})
.model xor d_xor
.MODEL D_FF d_dff (clk_delay={Clk_delay} set_delay={Set_delay} reset_delay={Reset_delay} ic={Ic} rise_delay={Rise_delay} fall_delay={Fall_delay})
.ENDS

* B subcircuit
.subckt Digital_DFlipFlop_B 1 2 3 4 5 6 PARAMS: Negative_Edge_Clock=0 Negative_SET_RESET=0 Clk_delay=1n Set_delay=1n Reset_delay=1n Ic=0 Rise_delay=1n Fall_delay=1n
*PIN MAPPING: D Q ~Q RESET CLK SET
* 1 5 6 4 2 3
*MODELS USED
aDG1 neg_SR Digital_SourceSR
aDG2 neg_clk Digital_SourceCLK
Axor1 [3 neg_SR] set xor
Axor2 [2 neg_clk] clk xor
Axor3 [4 neg_SR] reset xor
Ajkff 1 clk set reset 5 6 D_FF

.model Digital_SourceCLK d_constsource(State={Negative_Edge_Clock})
.model Digital_SourceSR d_constsource(State={Negative_SET_RESET})
.model xor d_xor
.MODEL D_FF d_dff (clk_delay={Clk_delay} set_delay={Set_delay} reset_delay={Reset_delay} ic={Ic} rise_delay={Rise_delay} fall_delay={Fall_delay})
.ENDS

* C subcircuit
.subckt Digital_DFlipFlop_C 1 2 3 4 5 6 PARAMS: Negative_Edge_Clock=0 Negative_SET_RESET=0 Clk_delay=1n Set_delay=1n Reset_delay=1n Ic=0 Rise_delay=1n Fall_delay=1n
*PIN MAPPING: D Q ~Q RESET CLK SET
* 1 5 6 4 2 3
*MODELS USED
aDG1 neg_SR Digital_SourceSR
aDG2 neg_clk Digital_SourceCLK
Axor1 [3 neg_SR] set xor
Axor2 [2 neg_clk] clk xor
Axor3 [4 neg_SR] reset xor
Ajkff 1 clk set reset 5 6 D_FF

.model Digital_SourceCLK d_constsource(State={Negative_Edge_Clock})
.model Digital_SourceSR d_constsource(State={Negative_SET_RESET})
.model xor d_xor
.MODEL D_FF d_dff (clk_delay={Clk_delay} set_delay={Set_delay} reset_delay={Reset_delay} ic={Ic} rise_delay={Rise_delay} fall_delay={Fall_delay})
.ENDS

* EN subcircuit
.subckt SPDT_Switch_EN port1 port2 port3 Params: Ron=1e-8 Roff=1e30 State=0
V2 state 0 DC {State}
R1 state 6 10
V1 6 0 DC 0
W0 port2 port1 V1 NC_contact
W1 port2 port3 V1 NO_contact
.MODEL NO_contact ISWITCH (ION=0.05 IOFF=0.025 RON={Ron} ROFF={Roff})
.MODEL NC_contact ISWITCH (ION=0.05 IOFF=0.025 RON={Roff} ROFF={Ron})
.ends

* U1 subcircuit
**********************
*74LS47 DECODER/DRIVER BCD-7 SEGMENT WITH
*OPEN-COLLECTOR OUTPUTS
***
.subckt 74LS47_U1 ina inb inc ind ltb rbib bib/rbob a d e f c b g PARAMS: Rise_delay=100n Fall_delay=100n
*FAMILY TTLin TTLin TTLin TTLin TTLin TTLin TTLin
*TTLout TTLout TTLout TTLout TTLout TTLout TTLout
*pinout N 7 1 2 6 13 10 9 15 11 12 14 3 5 4:VCC=16 GND=8
*pinout J 7 1 2 6 13 10 9 15 11 12 14 3 5 4:VCC=16 GND=8
*pinout D 7 1 2 6 13 10 9 15 11 12 14 3 5 4:VCC=16 GND=8

ainv1 rbib rbi inv

ananda1 [ina ltb] a1 nand
anandb1 [inb ltb] b1 nand
anandc1 [inc ltb] c1 nand
anandd1 [ind ind] d1 nand

ananda2 [a1 bib/rbob] a2 nand
anandb2 [b1 bib/rbob] b2 nand
anandc2 [c1 bib/rbob] c2 nand
anandd2 [d1 bib/rbob] d2 nand

anand6 [ltb rbi d1 c1 b1 a1] nandopenc nand

aopenc1 nandopenc bib/rbob open

aand1a [b2 d2] x1 and
aand2a [a1 c2] x2 and
aand3a [a2 b1 c1 d1] x3 and
aor1 [x1 x2 x3] ai or

aand1b [b2 d2] x4 and
aand2b [a2 b1 c2] x5 and
aand3b [a1 b2 c2] x6 and
aor2 [x4 x5 x6] bi or

aand1c [c2 d2] x7 and
aand2c [a1 b2 c1] x8 and
aor3 [x7 x8] ci or

aand1d [a2 b1 c1] x9 and
aand2d [a1 b1 c2] xa and
aand3d [a2 b2 c2] xb and
aor4 [x9 xa xb] di or

aand1e [b1 c2] xc and
aor5 [xc a2] ei or

aand1f [a2 b2] xd and
aand2f [b2 c1] xe and
aand3f [a2 c1 d1] xf and
aor6 [xd xe xf] fi or

aand1g [a2 b2 c2] xg and
aand2g [b1 c1 d1 ltb] xh and
aor7 [xg xh] gi or

aop1 ai a open
aop2 bi b open
aop3 ci c open
aop4 di d open
aop5 ei e open
aop6 fi f open
aop7 gi g open

.model inv d_inverter
.model nand d_nand
.model and d_and
.model or d_or(rise_delay={Rise_delay} fall_delay={Fall_delay})
.model open d_open_c

.ends

* U18 subcircuit
.subckt 7_SEGMENT_CA_U18 K1 K2 K3 K4 K5 K6 K7 A

dd1 A 0vNode1 ledDiodeModel
Vsense1 0vNode1 K1 DC 0
* Interactive sense node
b1 lit1 0 v = { if (i(Vsense1) < 0, 0, if( i(Vsense1) > 0.02, 1, { i(Vsense1) / 0.02 })) }

dd2 A 0vNode2 ledDiodeModel
Vsense2 0vNode2 K2 DC 0
* Interactive sense node
b2 lit2 0 v = { if (i(Vsense2) < 0, 0, if( i(Vsense2) > 0.02, 1, { i(Vsense2) / 0.02 })) }

dd3 A 0vNode3 ledDiodeModel
Vsense3 0vNode3 K3 DC 0
* Interactive sense node
b3 lit3 0 v = { if (i(Vsense3) < 0, 0, if( i(Vsense3) > 0.02, 1, { i(Vsense3) / 0.02 })) }

dd4 A 0vNode4 ledDiodeModel
Vsense4 0vNode4 K4 DC 0
* Interactive sense node
b4 lit4 0 v = { if (i(Vsense4) < 0, 0, if( i(Vsense4) > 0.02, 1, { i(Vsense4) / 0.02 })) }

dd5 A 0vNode5 ledDiodeModel
Vsense5 0vNode5 K5 DC 0
* Interactive sense node
b5 lit5 0 v = { if (i(Vsense5) < 0, 0, if( i(Vsense5) > 0.02, 1, { i(Vsense5) / 0.02 })) }

dd6 A 0vNode6 ledDiodeModel
Vsense6 0vNode6 K6 DC 0
* Interactive sense node
b6 lit6 0 v = { if (i(Vsense6) < 0, 0, if( i(Vsense6) > 0.02, 1, { i(Vsense6) / 0.02 })) }

dd7 A 0vNode7 ledDiodeModel
Vsense7 0vNode7 K7 DC 0
* Interactive sense node
b7 lit7 0 v = { if (i(Vsense7) < 0, 0, if( i(Vsense7) > 0.02, 1, { i(Vsense7) / 0.02 })) }

.model ledDiodeModel D( IS=1e-14 N=1 RS=0 IBV=1e-10 BV=1e+30 CJO=0 M=0.5 VJ=1 )
.ends

* --- Pin bridge models

.SUBCKT REAL_CUSTOM_DAC 1 2 PARAMS: lowV=0 maxLowV=0.8 unknownV=1.0 minHighV=2.0 highV=5.0 riseT=0 fallT=0
* Ideal Driver Model 1 = A/D out, 2 = input
aDACin1 [1] [2] aDAC
.MODEL aDAC dac_bridge (out_low = {lowV} out_high = {highV} out_undef = {unknownV} t_rise = {max(riseT,1e-9)} t_fall = {max(fallT,1e-9)})
.ENDS

.SUBCKT REAL_CUSTOM_ADC 1 2 PARAMS: lowV=0 maxLowV=0.8 unknownV=1.0 minHighV=2.0 highV=5.0 riseT=0 fallT=0
* Ideal Receiver Model 1 = input, 2 = A/D out
aADCin1 [2] [1] ADC
.MODEL ADC adc_bridge (in_low = {maxLowV} in_high = {minHighV})
.ENDS

Errors and Warnings

Any error, warning or information messages appear below.

Item

Document

Section

Only one section is available for multisection components.

Type

Rise time

Time it takes for signal to transition from low to high.

With non-zero rise time, the signal converts to an analog signal from a digital signal.

Fall time

Time it takes for signal to transition from high to low.

With non-zero fall time, the signal converts to an analog signal from a digital signal.

Use document settings

Use logic levels settings from Document tab.

Threshold voltage levels.

Threshold voltage values used in the logic evaluation. See Digital Simulation for more information.

Output low

Output low voltage.

Maximum output voltage level to produce a low signal.

Input low threshold

Input low threshold voltage.

Maximum input voltage level for the signal to be considered low.

Input high threshold

Input high threshold voltage.

Minimum input voltage level for the signal to be considered high.

Output high

Output high voltage.

Minimum output voltage level to produce a high signal.

Type Probe

Select desired function.

Function

Use document settings

Use logic levels settings from Document tab.

Threshold voltage levels.

Threshold voltage values used in the logic evaluation. See Digital Simulation for more information.

Output low

Output low voltage.

Maximum output voltage level to produce a low signal.

Input low threshold

Input low threshold voltage.

Maximum input voltage level for the signal to be considered low.

Input high threshold

Input high threshold voltage.

Minimum input voltage level for the signal to be considered high.

Output high

Output high voltage.

Minimum output voltage level to produce a high signal.

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Source

Data origin.

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Connect

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Connecting

Disconnect

Switch on to stream data from Source when simulation runs.

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Source type

Application used to generate the Source data.

Data type

Type of simulation data in Source.

File size

Size of the referenced file. Total file size for all data plotters cannot exceed 100 MB.

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Data streaming is only available in interactive simulation

Instantaneous

Displays instantaneous measurements on probe during interactive simulation.

Periodic

Displays periodic measurements on probe during Interactive simulation.

Bias point(s)

Displays bias points on probe for DC Op simulation.

No items selected.

Name 4.1.2-DOB_STATE_MACHINE-Diego Ayala

Type Schematic

The simulation to run. See Simulation types for more information.

Name

Title of graph. Edit as desired.

End time

Time at which the simulation stops. Does not include pauses. Simulation does not occur in real time.

Start simulation

RELTOL

Relative error tolerance. A simulation wide accuracy control used to establish convergence.

VNTOL

Absolute voltage error tolerance. Defines the minimum value for voltage where it may still be considered accurate.

ABSTOL

Absolute current error tolerance. Defines the minimum value for current where it may still be considered accurate.

ITL1

DC iteration limit. Number of iterative passes done on DC circuit equations in attempt to reach convergence in simulation.

ITL4

Upper iteration limit. Number of iterative passes done per time point, on Transient circuit equations in attempt to reach convergence in simulation.

Integration method. The numerical integration method used in transient analysis.

Temp

℃

Operating temperature. The temperature at which the entire circuit will be simulated.

Insert shunt resistance

Inserts a resistance of RSHUNT from every analog node to ground. Will aid in convergence, but alter the behavior of the circuit.

RSHUNT

Shunt resistance. This eliminates singular matrix errors that result from a lack of a DC path to ground.

Reset to default

Threshold voltage levels.

Threshold voltage values used in the logic evaluation. See Digital Simulation for more information.

Output low

Output low voltage.

Maximum output voltage level to produce a low signal.

Input low threshold

Input low threshold voltage.

Maximum input voltage level for the signal to be considered low.

Input high threshold

Input high threshold voltage.

Minimum input voltage level for the signal to be considered high.

Output high

Output high voltage.

Minimum output voltage level to produce a high signal.

Width

Sheet width in grid squares.

Height

Sheet height in grid squares.

Grid

Toggles grid display.

Net Labels

Toggles all net labels.

Component Labels

Toggles all component labels.

4.1.2-DOB_STATE_MACHINE-Diego Ayala