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MCR08BT1GD19V1kHz0°V112VX112.2kΩR12500kΩ28.5%R235kΩR34D250PR3PR1PR2PR4 VA VA VA VA
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ID:

ID:
x10
x0.1
Sheet:1
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** 3 **
*
* Multisim Live SPICE netlist
*
*

* --- Circuit Topology ---

* Component: D1
xD1 2 5 0 MCR08MT1/ON_D1

* Component: D2
dD2 4 5 DIODE_D2 AREA=1

* Component: R1
rR1 2 3 2200 VIRTUAL_RESISTANCE_R1

* Component: R2
xR2 4 3 3 Potentiometer_R2 PARAMS: res=500000 posPercent=28.5

* Component: R3
rR3 4 0 5000 VIRTUAL_RESISTANCE_R3

* Component: V1
vV1 1 0 dc 0 ac 1 0
+ distof1 0 0
+ distof2 0 0
+ sin ( 0 9 1000 0 0 0 )

* Component: X1
xX1 1 2 VIR_LAMP_X1


* --- Circuit Models ---

* D2 model
.model DIODE_D2 D( IS=1e-14 RS=0 N=1 BV=1e+30
+ TT=0 CJO=0 VJ=1 M=0.5 EG=1.11 XTI=3 KF=0 AF=1 FC=0.5 IBV=1e-10
+ IBVL=0 IKF=1e+30 ISR=0 NBV=1 NBVL=1 NR=2 TBV1=0 TBV2=0 TIKF=0
+ TRS1=0 TRS2=0
+ )

* R1 model
.model VIRTUAL_RESISTANCE_R1 r( )

* R3 model
.model VIRTUAL_RESISTANCE_R3 r( )


* --- Subcircuits ---

* D1 subcircuit
*$
.subckt MCR08MT1/ON_D1 anode gate cathode PARAMS:
**************************************
* Model Generated by EVAL LAB *
* July 23, 2003 *
* Copyright(c) On Semiconductor *
* All Rights Reserved *
*Commercial Use or Resale Restricted *
**************************************
*SCR
*MODEL FORMAT: PSpice
+ Vdrm=600v Vrrm=600v Idrm=10u
+ Ih=2.5ma dVdt=10e6
* Vgt must be greater than 0.65v
+ Igt=6.5ua Vgt=0.66v
+ Vtm=1.4v Itm=1.0
+ Ton=2u Toff=15u

* Where:
* Vdrm => Forward breakover voltage
* Vrrm => Reverse breakdown voltage
* Idrm => Peak blocking current
* Ih => Holding current
* dVdt => Critical value for dV/dt triggering
* Igt => Gate trigger current
* Vgt => Gate trigger voltage
* Vtm => On-state voltage
* Itm => On-state current
* Ton => Turn-on time
* Toff => Turn-off time

* Main conduction path
Scr anode anode0 control 0 Vswitch ; controlled switch
Dak1 anode0 anode2 Dakfwd OFF ; SCR is initially off
Dka cathode anode0 Dkarev OFF
VIak anode2 cathode ; current sensor

* dVdt Turn-on
Emon dvdt0 0 TABLE {v(anode,cathode)} (0 0) (2000 2000)
CdVdt dvdt0 dvdt1 100pfd ; displacement current
Rdlay dvdt1 dvdt2 1k
VdVdt dvdt2 cathode DC 0.0
EdVdt condvdt 0 TABLE {i(vdVdt)-100p*dVdt} (0 0 ) (.1m 10)
RdVdt condvdt 0 1meg

* Gate
Rseries gate gate1 {(Vgt-0.65)/Igt}
Rshunt gate1 gate2 {0.65/Igt}
Dgkf gate1 gate2 Dgk
VIgf gate2 cathode ; current sensor

* Gate Turn-on
Egate1 gate4 0 TABLE {i(Vigf)-0.95*Igt} (0 0) (1m 10)
Rgate1 gate4 0 1meg
Egon1 congate 0 TABLE {v(gate4)*v(anode,cathode)} (0 0) (10 10)
Rgon1 congate 0 1meg

* Main Turn-on
EItot Itot 0 TABLE {i(VIak)+5E-5*i(VIgf)/Igt} (0 0) (2000 2000)
RItot Itot 0 1meg
Eprod prod 0 TABLE {v(anode,cathode)*v(Itot)} (0 0) (1 1)
Rprod prod 0 1meg
Elin conmain 0 TABLE
+ {10*(v(prod) - (Vtm*Ih))/(Vtm*Ih)} (0 0) (2 10)
Rlin conmain 0 1meg

* Turn-on/Turn-off control
Eonoff contot 0 TABLE
+ {v(congate)+v(conmain)+v(condvdt)} (0 0) (10 10)

* Turn-on/Turn-off delays
Rton contot dlay1 825
Dton dlay1 control Delay
Rtoff contot dlay2 {290*Toff/Ton}
Dtoff control dlay2 Delay
Cton control 0 {Ton/454}

* Reverse breakdown
Dbreak anode break1 Dbreak
Dbreak2 cathode break1 Dseries

* Controlled switch model
.MODEL Vswitch vswitch
+ (Ron = {(Vtm-0.7)/Itm}, Roff = {Vdrm*Vdrm/(Vtm*Ih)},
+ Von = 5.0, Voff = 1.5)

* Diodes
.MODEL Dgk D (Is=1E-16 Cjo=50pf Rs=5)
.MODEL Dseries D (Is=1E-14)
.MODEL Delay D (Is=1E-12 Cjo=5pf Rs=0.01)
.MODEL Dkarev D (Is=1E-10 Cjo=5pf Rs=0.01)
.MODEL Dakfwd D (Is=4E-11 Cjo=5pf)
.MODEL Dbreak D (Ibv=1E-7 Bv={1.1*Vrrm} Cjo=5pf Rs=0.5)

* Allow the gate to float if required
Rfloat gate cathode 1e10

.ENDS

* R2 subcircuit
.subckt Potentiometer_R2 T1 T2 T3 PARAMS: res=10k posPercent=50
.PARAM relPos = limit(posPercent * 0.01, 0.0000001, 0.9999999)
r1 T1 T2 {{res}*relPos}
r2 T2 T3 {{res} - {res}*relPos}
.ends

* X1 subcircuit
.subckt VIR_LAMP_X1 port1 port2

** resistance of the lamp when conducting current
.param lampResistance = {12^2/10}

** resistance of the lamp after burning out
.param blownResistance = 10e6

** blown signal appears on node blown. 5V = blown, 0 = not
Rdummy blown 0 1000000

** Constant digital high to feed as input to latch
aU2 dU1.DATA d_constsource_U2
.model d_constsource_U2 d_constsource(state=1)

**D-latch to latch state
aU1 dU1.DATA
+ dU1.EN
+ U1_OPEN_SET
+ U1_OPEN_RESET
+ dU1.Q
+ U1_OPEN_notQ D_LATCH

** Output of latch onto node `blown` through DAC
xU1.Q dU1.Q blown TIL_DRV

** Input node `trigger` to latch ENABLE through ADC
xU1.CLK trigger dU1.EN TIL_RCV

** If over blown voltage, trigger DLATCH U1 enable
E2 trigger 0 Value = { if(abs(V(port1, port2)) > 15 & Time > 0, 5, 0) }

** Modelling LIT and HOT states
blit lit 0 v={if(abs(V(port1, port2)) <= 12, {abs(V(port1, port2)) / 12}, 1)}
bhot hot 0 v={abs(V(port1, port2)) >= 12}

** Current sensor
V_Isense port1 lampSense 0

** model of the lamp as a G source so we can change the resistance on the fly
G_Lamp lampSense port2 value = { if( V(blown) < 2.5, V(port1, port2) / lampResistance, V(port1, port2) / blownResistance )}

.subckt TIL_DRV 1 2
* TIL Driver Model 1= D/A input, 2 = out
aDACin1 [1] [2] aDAC
.model aDAC dac_bridge (out_low = 0 out_high = 5 out_undef = 2.5)
.ends

.subckt TIL_RCV 1 2
* TIL Receiver Model 1 = input, 2 = A/D out
aADCin1 [1] [2] ADC
.model ADC adc_bridge (in_low = 2.5 in_high = 2.5)
.ends

.model D_LATCH d_dlatch (data_delay = 1n enable_delay = 1n
+ set_delay = 1n reset_delay = 1n
+ ic = 0 rise_delay = 1n fall_delay = 1n)

.ends
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