*Design dynamic CMOS logic 3-input XNOR and extract its netlist

Waiting for data

Signal	Value
Signal	Value

Cursor 1	Cursor 2	∆X	1/∆X	∆Y	∆Y (Phase)

Out of date
V	—
V	—
V_PP	—
V_RMS	—
V_AV	—
f_V	—
I	—
I	—
I_PP	—
I_RMS	—
I_AV	—
f_I	—
D	—

ID:

x10

x0.1

Sheet:1

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SPICE

SPICE Netlist

This is a text-based representation of the circuit.
The * symbol indicates a comment.
The + symbol indicates a continuation from the previous line.
Probes do not appear in netlists.

** Design dynamic CMOS logic 3-input XNOR and extract its netlist **
*
* Multisim Live SPICE netlist
*
*

* --- Circuit Topology ---

* Component: Q1
mQ1 12 Xbar 1 1 NMOS_Q1 L=1.8e-7 W=0.000002 M=1 AD=0 AS=0 PD=0 PS=0 NRD=1 NRS=1

* Component: Q10
mQ10 6 W 0 0 NMOS_Q10 L=1.8e-7 W=0.000002 M=1 AD=0 AS=0 PD=0 PS=0 NRD=1 NRS=1

* Component: Q11
mQ11 8 Xbar 5 5 PMOS_Q11 L=1.8e-7 W=0.000004 M=1 AD=0 AS=0 PD=0 PS=0 NRD=1 NRS=1

* Component: Q12
mQ12 7 X 8 8 PMOS_Q12 L=1.8e-7 W=0.000004 M=1 AD=0 AS=0 PD=0 PS=0 NRD=1 NRS=1

* Component: Q13
mQ13 11 X 7 7 PMOS_Q13 L=1.8e-7 W=0.000004 M=1 AD=0 AS=0 PD=0 PS=0 NRD=1 NRS=1

* Component: Q14
mQ14 12 Xbar 11 11 PMOS_Q14 L=1.8e-7 W=0.000004 M=1 AD=0 AS=0 PD=0 PS=0 NRD=1 NRS=1

* Component: Q15
mQ15 8 Y 5 5 PMOS_Q15 L=1.8e-7 W=0.000004 M=1 AD=0 AS=0 PD=0 PS=0 NRD=1 NRS=1

* Component: Q16
mQ16 7 Ybar 8 8 PMOS_Q16 L=1.8e-7 W=0.000004 M=1 AD=0 AS=0 PD=0 PS=0 NRD=1 NRS=1

* Component: Q17
mQ17 11 Y 7 7 PMOS_Q17 L=1.8e-7 W=0.000004 M=1 AD=0 AS=0 PD=0 PS=0 NRD=1 NRS=1

* Component: Q18
mQ18 12 Ybar 11 11 PMOS_Q18 L=1.8e-7 W=0.000004 M=1 AD=0 AS=0 PD=0 PS=0 NRD=1 NRS=1

* Component: Q19
mQ19 7 Wbar 5 5 PMOS_Q19 L=1.8e-7 W=0.000004 M=1 AD=0 AS=0 PD=0 PS=0 NRD=1 NRS=1

* Component: Q2
mQ2 1 Y 3 3 NMOS_Q2 L=1.8e-7 W=0.000002 M=1 AD=0 AS=0 PD=0 PS=0 NRD=1 NRS=1

* Component: Q20
mQ20 12 W 7 7 PMOS_Q20 L=1.8e-7 W=0.000004 M=1 AD=0 AS=0 PD=0 PS=0 NRD=1 NRS=1

* Component: Q3
mQ3 12 X 4 4 NMOS_Q3 L=1.8e-7 W=0.000002 M=1 AD=0 AS=0 PD=0 PS=0 NRD=1 NRS=1

* Component: Q4
mQ4 4 Ybar 3 3 NMOS_Q4 L=1.8e-7 W=0.000002 M=1 AD=0 AS=0 PD=0 PS=0 NRD=1 NRS=1

* Component: Q5
mQ5 3 Wbar 0 0 NMOS_Q5 L=1.8e-7 W=0.000002 M=1 AD=0 AS=0 PD=0 PS=0 NRD=1 NRS=1

* Component: Q6
mQ6 12 X Q6_NC_S Q6_NC_S NMOS_Q6 L=1.8e-7 W=0.000002 M=1 AD=0 AS=0 PD=0 PS=0 NRD=1 NRS=1

* Component: Q7
mQ7 Q7_NC_D Y 6 6 NMOS_Q7 L=1.8e-7 W=0.000002 M=1 AD=0 AS=0 PD=0 PS=0 NRD=1 NRS=1

* Component: Q8
mQ8 12 Xbar Q8_NC_S Q8_NC_S NMOS_Q8 L=1.8e-7 W=0.000002 M=1 AD=0 AS=0 PD=0 PS=0 NRD=1 NRS=1

* Component: Q9
mQ9 Q9_NC_D Ybar 6 6 NMOS_Q9 L=1.8e-7 W=0.000002 M=1 AD=0 AS=0 PD=0 PS=0 NRD=1 NRS=1

* Component: U1
aU1 bridgeU1!A bridgeU1!Y Digital_Inverter_U1

xbridgeU1!A bridgeU1!A X REAL_CUSTOM_ADC PARAMS: lowV=0 maxLowV=0.8 unknownV=1 minHighV=2 highV=3.3 riseT=0 fallT=0

xbridgeU1!Y bridgeU1!Y Xbar REAL_CUSTOM_DAC PARAMS: lowV=0 maxLowV=0.8 unknownV=1 minHighV=2 highV=3.3 riseT=0 fallT=0

* Component: U2
aU2 bridgeU2!A bridgeU2!Y Digital_Inverter_U2

xbridgeU2!A bridgeU2!A Y REAL_CUSTOM_ADC PARAMS: lowV=0 maxLowV=0.8 unknownV=1 minHighV=2 highV=3.3 riseT=0 fallT=0

xbridgeU2!Y bridgeU2!Y Ybar REAL_CUSTOM_DAC PARAMS: lowV=0 maxLowV=0.8 unknownV=1 minHighV=2 highV=3.3 riseT=0 fallT=0

* Component: U3
aU3 bridgeU3!A bridgeU3!Y Digital_Inverter_U3

xbridgeU3!A bridgeU3!A W REAL_CUSTOM_ADC PARAMS: lowV=0 maxLowV=0.8 unknownV=1 minHighV=2 highV=3.3 riseT=0 fallT=0

xbridgeU3!Y bridgeU3!Y Wbar REAL_CUSTOM_DAC PARAMS: lowV=0 maxLowV=0.8 unknownV=1 minHighV=2 highV=3.3 riseT=0 fallT=0

* Component: V1
vV1 5 0 dc 3.3 ac 0 0
+ distof1 0 0
+ distof2 0 0

* --- Circuit Models ---

* Q1 model
.model NMOS_Q1 NMOS( Level=1
+VTO=0.7 KP=0.00045 LAMBDA=0 RD=0 RS=0
+ IS=1e-14 PB=0.8 CGSO=0 CGDO=0 CGBO=0 MJ=0.5
+ MJSW=0.33 JS=0 NSS=0 TPG=1 LD=0 U0=600 KF=0
+AF=1 FC=0.5 RG=0 RB=0 RDS=0 WD=0 N=1 JSSW=0
+TT=0 NLEV=2 GDSNOI=1
+ )

* Q10 model
.model NMOS_Q10 NMOS( Level=1
+VTO=0.7 KP=0.00045 LAMBDA=0 RD=0 RS=0
+ IS=1e-14 PB=0.8 CGSO=0 CGDO=0 CGBO=0 MJ=0.5
+ MJSW=0.33 JS=0 NSS=0 TPG=1 LD=0 U0=600 KF=0
+AF=1 FC=0.5 RG=0 RB=0 RDS=0 WD=0 N=1 JSSW=0
+TT=0 NLEV=2 GDSNOI=1
+ )

* Q11 model
.model PMOS_Q11 PMOS( Level=1
+VTO=-0.7 KP=0.00015 LAMBDA=0 RD=0 RS=0
+ IS=1e-14 PB=0.8 CGSO=0 CGDO=0 CGBO=0 MJ=0.5
+ MJSW=0.33 JS=0 NSS=0 TPG=1 LD=0 U0=600 KF=0
+AF=1 FC=0.5 RG=0 RB=0 RDS=0 WD=0 N=1 JSSW=0
+TT=0 NLEV=2 GDSNOI=1
+ )

* Q12 model
.model PMOS_Q12 PMOS( Level=1
+VTO=-0.7 KP=0.00015 LAMBDA=0 RD=0 RS=0
+ IS=1e-14 PB=0.8 CGSO=0 CGDO=0 CGBO=0 MJ=0.5
+ MJSW=0.33 JS=0 NSS=0 TPG=1 LD=0 U0=600 KF=0
+AF=1 FC=0.5 RG=0 RB=0 RDS=0 WD=0 N=1 JSSW=0
+TT=0 NLEV=2 GDSNOI=1
+ )

* Q13 model
.model PMOS_Q13 PMOS( Level=1
+VTO=-0.7 KP=0.00015 LAMBDA=0 RD=0 RS=0
+ IS=1e-14 PB=0.8 CGSO=0 CGDO=0 CGBO=0 MJ=0.5
+ MJSW=0.33 JS=0 NSS=0 TPG=1 LD=0 U0=600 KF=0
+AF=1 FC=0.5 RG=0 RB=0 RDS=0 WD=0 N=1 JSSW=0
+TT=0 NLEV=2 GDSNOI=1
+ )

* Q14 model
.model PMOS_Q14 PMOS( Level=1
+VTO=-0.7 KP=0.00015 LAMBDA=0 RD=0 RS=0
+ IS=1e-14 PB=0.8 CGSO=0 CGDO=0 CGBO=0 MJ=0.5
+ MJSW=0.33 JS=0 NSS=0 TPG=1 LD=0 U0=600 KF=0
+AF=1 FC=0.5 RG=0 RB=0 RDS=0 WD=0 N=1 JSSW=0
+TT=0 NLEV=2 GDSNOI=1
+ )

* Q15 model
.model PMOS_Q15 PMOS( Level=1
+VTO=-0.7 KP=0.00015 LAMBDA=0 RD=0 RS=0
+ IS=1e-14 PB=0.8 CGSO=0 CGDO=0 CGBO=0 MJ=0.5
+ MJSW=0.33 JS=0 NSS=0 TPG=1 LD=0 U0=600 KF=0
+AF=1 FC=0.5 RG=0 RB=0 RDS=0 WD=0 N=1 JSSW=0
+TT=0 NLEV=2 GDSNOI=1
+ )

* Q16 model
.model PMOS_Q16 PMOS( Level=1
+VTO=-0.7 KP=0.00015 LAMBDA=0 RD=0 RS=0
+ IS=1e-14 PB=0.8 CGSO=0 CGDO=0 CGBO=0 MJ=0.5
+ MJSW=0.33 JS=0 NSS=0 TPG=1 LD=0 U0=600 KF=0
+AF=1 FC=0.5 RG=0 RB=0 RDS=0 WD=0 N=1 JSSW=0
+TT=0 NLEV=2 GDSNOI=1
+ )

* Q17 model
.model PMOS_Q17 PMOS( Level=1
+VTO=-0.7 KP=0.00015 LAMBDA=0 RD=0 RS=0
+ IS=1e-14 PB=0.8 CGSO=0 CGDO=0 CGBO=0 MJ=0.5
+ MJSW=0.33 JS=0 NSS=0 TPG=1 LD=0 U0=600 KF=0
+AF=1 FC=0.5 RG=0 RB=0 RDS=0 WD=0 N=1 JSSW=0
+TT=0 NLEV=2 GDSNOI=1
+ )

* Q18 model
.model PMOS_Q18 PMOS( Level=1
+VTO=-0.7 KP=0.00015 LAMBDA=0 RD=0 RS=0
+ IS=1e-14 PB=0.8 CGSO=0 CGDO=0 CGBO=0 MJ=0.5
+ MJSW=0.33 JS=0 NSS=0 TPG=1 LD=0 U0=600 KF=0
+AF=1 FC=0.5 RG=0 RB=0 RDS=0 WD=0 N=1 JSSW=0
+TT=0 NLEV=2 GDSNOI=1
+ )

* Q19 model
.model PMOS_Q19 PMOS( Level=1
+VTO=-0.7 KP=0.00015 LAMBDA=0 RD=0 RS=0
+ IS=1e-14 PB=0.8 CGSO=0 CGDO=0 CGBO=0 MJ=0.5
+ MJSW=0.33 JS=0 NSS=0 TPG=1 LD=0 U0=600 KF=0
+AF=1 FC=0.5 RG=0 RB=0 RDS=0 WD=0 N=1 JSSW=0
+TT=0 NLEV=2 GDSNOI=1
+ )

* Q2 model
.model NMOS_Q2 NMOS( Level=1
+VTO=0.7 KP=0.00045 LAMBDA=0 RD=0 RS=0
+ IS=1e-14 PB=0.8 CGSO=0 CGDO=0 CGBO=0 MJ=0.5
+ MJSW=0.33 JS=0 NSS=0 TPG=1 LD=0 U0=600 KF=0
+AF=1 FC=0.5 RG=0 RB=0 RDS=0 WD=0 N=1 JSSW=0
+TT=0 NLEV=2 GDSNOI=1
+ )

* Q20 model
.model PMOS_Q20 PMOS( Level=1
+VTO=-0.7 KP=0.00015 LAMBDA=0 RD=0 RS=0
+ IS=1e-14 PB=0.8 CGSO=0 CGDO=0 CGBO=0 MJ=0.5
+ MJSW=0.33 JS=0 NSS=0 TPG=1 LD=0 U0=600 KF=0
+AF=1 FC=0.5 RG=0 RB=0 RDS=0 WD=0 N=1 JSSW=0
+TT=0 NLEV=2 GDSNOI=1
+ )

* Q3 model
.model NMOS_Q3 NMOS( Level=1
+VTO=0.7 KP=0.00045 LAMBDA=0 RD=0 RS=0
+ IS=1e-14 PB=0.8 CGSO=0 CGDO=0 CGBO=0 MJ=0.5
+ MJSW=0.33 JS=0 NSS=0 TPG=1 LD=0 U0=600 KF=0
+AF=1 FC=0.5 RG=0 RB=0 RDS=0 WD=0 N=1 JSSW=0
+TT=0 NLEV=2 GDSNOI=1
+ )

* Q4 model
.model NMOS_Q4 NMOS( Level=1
+VTO=0.7 KP=0.00045 LAMBDA=0 RD=0 RS=0
+ IS=1e-14 PB=0.8 CGSO=0 CGDO=0 CGBO=0 MJ=0.5
+ MJSW=0.33 JS=0 NSS=0 TPG=1 LD=0 U0=600 KF=0
+AF=1 FC=0.5 RG=0 RB=0 RDS=0 WD=0 N=1 JSSW=0
+TT=0 NLEV=2 GDSNOI=1
+ )

* Q5 model
.model NMOS_Q5 NMOS( Level=1
+VTO=0.7 KP=0.00045 LAMBDA=0 RD=0 RS=0
+ IS=1e-14 PB=0.8 CGSO=0 CGDO=0 CGBO=0 MJ=0.5
+ MJSW=0.33 JS=0 NSS=0 TPG=1 LD=0 U0=600 KF=0
+AF=1 FC=0.5 RG=0 RB=0 RDS=0 WD=0 N=1 JSSW=0
+TT=0 NLEV=2 GDSNOI=1
+ )

* Q6 model
.model NMOS_Q6 NMOS( Level=1
+VTO=0.7 KP=0.00045 LAMBDA=0 RD=0 RS=0
+ IS=1e-14 PB=0.8 CGSO=0 CGDO=0 CGBO=0 MJ=0.5
+ MJSW=0.33 JS=0 NSS=0 TPG=1 LD=0 U0=600 KF=0
+AF=1 FC=0.5 RG=0 RB=0 RDS=0 WD=0 N=1 JSSW=0
+TT=0 NLEV=2 GDSNOI=1
+ )

* Q7 model
.model NMOS_Q7 NMOS( Level=1
+VTO=0.7 KP=0.00045 LAMBDA=0 RD=0 RS=0
+ IS=1e-14 PB=0.8 CGSO=0 CGDO=0 CGBO=0 MJ=0.5
+ MJSW=0.33 JS=0 NSS=0 TPG=1 LD=0 U0=600 KF=0
+AF=1 FC=0.5 RG=0 RB=0 RDS=0 WD=0 N=1 JSSW=0
+TT=0 NLEV=2 GDSNOI=1
+ )

* Q8 model
.model NMOS_Q8 NMOS( Level=1
+VTO=0.7 KP=0.00045 LAMBDA=0 RD=0 RS=0
+ IS=1e-14 PB=0.8 CGSO=0 CGDO=0 CGBO=0 MJ=0.5
+ MJSW=0.33 JS=0 NSS=0 TPG=1 LD=0 U0=600 KF=0
+AF=1 FC=0.5 RG=0 RB=0 RDS=0 WD=0 N=1 JSSW=0
+TT=0 NLEV=2 GDSNOI=1
+ )

* Q9 model
.model NMOS_Q9 NMOS( Level=1
+VTO=0.7 KP=0.00045 LAMBDA=0 RD=0 RS=0
+ IS=1e-14 PB=0.8 CGSO=0 CGDO=0 CGBO=0 MJ=0.5
+ MJSW=0.33 JS=0 NSS=0 TPG=1 LD=0 U0=600 KF=0
+AF=1 FC=0.5 RG=0 RB=0 RDS=0 WD=0 N=1 JSSW=0
+TT=0 NLEV=2 GDSNOI=1
+ )

* U1 model
.model Digital_Inverter_U1 d_inverter (rise_delay=1e-9 fall_delay=1e-9)

* U2 model
.model Digital_Inverter_U2 d_inverter (rise_delay=1e-9 fall_delay=1e-9)

* U3 model
.model Digital_Inverter_U3 d_inverter (rise_delay=1e-9 fall_delay=1e-9)

* --- Pin bridge models

.SUBCKT REAL_CUSTOM_ADC 1 2 PARAMS: lowV=0 maxLowV=0.8 unknownV=1.0 minHighV=2.0 highV=5.0 riseT=0 fallT=0
* Ideal Receiver Model 1 = input, 2 = A/D out
aADCin1 [2] [1] ADC
.MODEL ADC adc_bridge (in_low = {maxLowV} in_high = {minHighV})
.ENDS

.SUBCKT REAL_CUSTOM_DAC 1 2 PARAMS: lowV=0 maxLowV=0.8 unknownV=1.0 minHighV=2.0 highV=5.0 riseT=0 fallT=0
* Ideal Driver Model 1 = A/D out, 2 = input
aDACin1 [1] [2] aDAC
.MODEL aDAC dac_bridge (out_low = {lowV} out_high = {highV} out_undef = {unknownV} t_rise = {max(riseT,1e-9)} t_fall = {max(fallT,1e-9)})
.ENDS

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Item

Document

Section

Only one section is available for multisection components.

Type

Rise time

Time it takes for signal to transition from low to high.

With non-zero rise time, the signal converts to an analog signal from a digital signal.

Fall time

Time it takes for signal to transition from high to low.

With non-zero fall time, the signal converts to an analog signal from a digital signal.

Use document settings

Use logic levels settings from Document tab.

Threshold voltage levels.

Threshold voltage values used in the logic evaluation. See Digital Simulation for more information.

Output low

Output low voltage.

Maximum output voltage level to produce a low signal.

Input low threshold

Input low threshold voltage.

Maximum input voltage level for the signal to be considered low.

Input high threshold

Input high threshold voltage.

Minimum input voltage level for the signal to be considered high.

Output high

Output high voltage.

Minimum output voltage level to produce a high signal.

Type Probe

Select desired function.

Function

Use document settings

Use logic levels settings from Document tab.

Threshold voltage levels.

Threshold voltage values used in the logic evaluation. See Digital Simulation for more information.

Output low

Output low voltage.

Maximum output voltage level to produce a low signal.

Input low threshold

Input low threshold voltage.

Maximum input voltage level for the signal to be considered low.

Input high threshold

Input high threshold voltage.

Minimum input voltage level for the signal to be considered high.

Output high

Output high voltage.

Minimum output voltage level to produce a high signal.

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Source

Data origin.

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Web address of the selected Source.

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Connect

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Connecting

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Source type

Application used to generate the Source data.

Data type

Type of simulation data in Source.

File size

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Instantaneous

Displays instantaneous measurements on probe during interactive simulation.

Periodic

Displays periodic measurements on probe during Interactive simulation.

Bias point(s)

Displays bias points on probe for DC Op simulation.

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Name Design dynamic CMOS logic 3-input XNOR and extract its netlist

Type Schematic

The simulation to run. See Simulation types for more information.

Name

Title of graph. Edit as desired.

End time

Time at which the simulation stops. Does not include pauses. Simulation does not occur in real time.

Start simulation

RELTOL

Relative error tolerance. A simulation wide accuracy control used to establish convergence.

VNTOL

Absolute voltage error tolerance. Defines the minimum value for voltage where it may still be considered accurate.

ABSTOL

Absolute current error tolerance. Defines the minimum value for current where it may still be considered accurate.

ITL1

DC iteration limit. Number of iterative passes done on DC circuit equations in attempt to reach convergence in simulation.

ITL4

Upper iteration limit. Number of iterative passes done per time point, on Transient circuit equations in attempt to reach convergence in simulation.

Integration method. The numerical integration method used in transient analysis.

Temp

℃

Operating temperature. The temperature at which the entire circuit will be simulated.

Insert shunt resistance

Inserts a resistance of RSHUNT from every analog node to ground. Will aid in convergence, but alter the behavior of the circuit.

RSHUNT

Shunt resistance. This eliminates singular matrix errors that result from a lack of a DC path to ground.

Reset to default

Threshold voltage levels.

Threshold voltage values used in the logic evaluation. See Digital Simulation for more information.

Output low

Output low voltage.

Maximum output voltage level to produce a low signal.

Input low threshold

Input low threshold voltage.

Maximum input voltage level for the signal to be considered low.

Input high threshold

Input high threshold voltage.

Minimum input voltage level for the signal to be considered high.

Output high

Output high voltage.

Minimum output voltage level to produce a high signal.

Width

Sheet width in grid squares.

Height

Sheet height in grid squares.

Grid

Toggles grid display.

Net Labels

Toggles all net labels.

Component Labels

Toggles all component labels.

Design dynamic CMOS logic 3-input XNOR and extract its netlist