Waiting for data
α Ph+ T1 Ph- T2 120V60Hz0°V1U1SCR_A10.0ΩR1100mHL145VV280SCR_A1SCR_A2SCR_A31205634PR1PR2PR3PR4 V V V V
Out of date
V —
V —
VPP —
VRMS —
VAV —
fV —
I —
I —
IPP —
IRMS —
IAV —
fI —
D —
Out of date
V —
V —
VPP —
VRMS —
VAV —
fV —
I —
I —
IPP —
IRMS —
IAV —
fI —
D —
Out of date
V —
V —
VPP —
VRMS —
VAV —
fV —
I —
I —
IPP —
IRMS —
IAV —
fI —
D —
Out of date
V —
V —
VPP —
VRMS —
VAV —
fV —
I —
I —
IPP —
IRMS —
IAV —
fI —
D —

ID:

ID:
x10
x0.1
Sheet:1
Disable streaming
Details
Netlist
Errors
Circuit Details

View and edit circuit details below.
Visibility
Private
Public

Select Public if you want your design to be viewable by all Multisim Live users.

Name

Name of saved file.

Description

Provides context to the design, and an explanation of the circuit operation. This is useful for highlighting theory or critical aspects of the design.
systems
x
ac circuits
x
add a tag

Type a string here. Matching tags appear as you type. Tap a matching tag, or enter a new tag.

SPICE
SPICE Netlist

This is a text-based representation of the circuit.
The * symbol indicates a comment.
The + symbol indicates a continuation from the previous line.
Probes do not appear in netlists.

** Controlled Rectifier **
*
* Multisim Live SPICE netlist
*
*

* --- Circuit Topology ---

* Component: L1
lL1 1 4 0.1

* Component: R1
rR1 4 2 10 VIRTUAL_RESISTANCE_R1

* Component: SCR_A
xSCR_A 3 1 5 SCR_IDEAL_SCR_A PARAMS: Vth=2.5 Ih=0.01 Vfscr=0 Ron=0.01 Roff=10000000

* Component: SCR_A1
xSCR_A1 0 1 6 SCR_IDEAL_SCR_A1 PARAMS: Vth=2.5 Ih=0.01 Vfscr=0 Ron=0.01 Roff=10000000

* Component: SCR_A2
xSCR_A2 2 3 6 SCR_IDEAL_SCR_A2 PARAMS: Vth=2.5 Ih=0.01 Vfscr=0 Ron=0.01 Roff=10000000

* Component: SCR_A3
xSCR_A3 2 0 5 SCR_IDEAL_SCR_A3 PARAMS: Vth=2.5 Ih=0.01 Vfscr=0 Ron=0.01 Roff=10000000

* Component: U1
xU1 3 0 8 5 6 PHASEANGLE_FULL_U1 PARAMS: frequency=60 pulse_width=20 pulse_amplitude=120

* Component: V1
vV1 3 0 dc 0 ac 1 0
+ distof1 0 0
+ distof2 0 0
+ sin ( 0 120 60 0 0 0 )

* Component: V2
vV2 8 0 dc 45 ac 0 0
+ distof1 0 0
+ distof2 0 0


* --- Circuit Models ---

* R1 model
.model VIRTUAL_RESISTANCE_R1 r( )


* --- Subcircuits ---

* SCR_A subcircuit
.subckt SCR_IDEAL_SCR_A Anode Cathode Gate PARAMS: Vth=2.5 Ih=0 Vfscr=0 Ron=1m Roff=1meg
E3 a2 0 Value = { if(I(vIscr)<=Ih,5,0) }

vIscr Anode 10 dc 0



xU6 8 cathode DIODE_IDEAL params: Vf={Vfscr} Rd={Ron/2} Rdoff={Roff/2}
.subckt DIODE_IDEAL a k params: Vf=0 Rd=1m Rdoff=1meg
ad1 %vd(a k) %id(a k) diode1
.model diode1 pwl(x_array=[{Vf-1} {Vf} {Vf+1}] y_array=[{-1/Rdoff} 0 {1/Rd}] fraction=false input_domain=0.0)
.ends


xS1 10 8 a3 0 VSwitchS1
.subckt VSwitchS1 1 2 3 4
S1 1 2 3 4 vsw0
.model vsw0 vswitch ( Roff={Roff/2} Ron={Ron/2} Voff=0 Von=1 )
.ends


aU5 7 d_constsource_U5
.model d_constsource_U5 d_constsource(state=1)


aU4 [a1 dU4.B dU4.C] reset AND2__TIL__1
xU4.B a2 dU4.B TIL_RCV__NON__1
xU4.C a3 dU4.C TIL_RCV__NON__1
aU3 dU3.A a1 NOT__TIL__1

xU3.A gate dU3.A TIL_RCV__NON__1_Gate

aU2 dU2.S reset 7
+ U2_OPEN_SET U2_OPEN_RESET
+ dU2.Q U2_OPEN_notQ SR_LATCH__TIL__1

xU2.S gate dU2.S TIL_RCV__NON__1_Gate


xU2.Q dU2.Q a3 TIL_DRV__NON__1



.MODEL AND2__TIL__1 d_and ( rise_delay = 1n fall_delay = 1n)
.MODEL NOT__TIL__1 d_inverter (rise_delay = 1n fall_delay = 1n)
.SUBCKT TIL_DRV__NON__1 1 2
* TIL Driver Model 1 = D/A input, 2 = out
aDACin1 [1] [2] aDAC
.MODEL aDAC dac_bridge (out_low= 0 out_high = 5 out_undef = 0)
.ENDS

.SUBCKT TIL_RCV__NON__1_Gate 1 2
* TIL Receiver Model 1 = input, 2 = A/D out
aADCin1 [1] [2] ADC
.MODEL ADC adc_bridge (in_low= {Vth} in_high = {Vth})
.ENDS

.SUBCKT TIL_RCV__NON__1 1 2
* TIL Receiver Model 1 = input, 2 = A/D out
aADCin1 [1] [2] ADC
.MODEL ADC adc_bridge (in_low= 2.5 in_high = 2.5)
.ENDS


.MODEL SR_LATCH__TIL__1 d_srlatch (sr_delay = 1n enable_delay = 1n
+ set_delay = 1n reset_delay= 1n
+ ic = 0 rise_delay = 1n fall_delay = 1n)

.ends

* SCR_A1 subcircuit
.subckt SCR_IDEAL_SCR_A1 Anode Cathode Gate PARAMS: Vth=2.5 Ih=0 Vfscr=0 Ron=1m Roff=1meg
E3 a2 0 Value = { if(I(vIscr)<=Ih,5,0) }

vIscr Anode 10 dc 0



xU6 8 cathode DIODE_IDEAL params: Vf={Vfscr} Rd={Ron/2} Rdoff={Roff/2}
.subckt DIODE_IDEAL a k params: Vf=0 Rd=1m Rdoff=1meg
ad1 %vd(a k) %id(a k) diode1
.model diode1 pwl(x_array=[{Vf-1} {Vf} {Vf+1}] y_array=[{-1/Rdoff} 0 {1/Rd}] fraction=false input_domain=0.0)
.ends


xS1 10 8 a3 0 VSwitchS1
.subckt VSwitchS1 1 2 3 4
S1 1 2 3 4 vsw0
.model vsw0 vswitch ( Roff={Roff/2} Ron={Ron/2} Voff=0 Von=1 )
.ends


aU5 7 d_constsource_U5
.model d_constsource_U5 d_constsource(state=1)


aU4 [a1 dU4.B dU4.C] reset AND2__TIL__1
xU4.B a2 dU4.B TIL_RCV__NON__1
xU4.C a3 dU4.C TIL_RCV__NON__1
aU3 dU3.A a1 NOT__TIL__1

xU3.A gate dU3.A TIL_RCV__NON__1_Gate

aU2 dU2.S reset 7
+ U2_OPEN_SET U2_OPEN_RESET
+ dU2.Q U2_OPEN_notQ SR_LATCH__TIL__1

xU2.S gate dU2.S TIL_RCV__NON__1_Gate


xU2.Q dU2.Q a3 TIL_DRV__NON__1



.MODEL AND2__TIL__1 d_and ( rise_delay = 1n fall_delay = 1n)
.MODEL NOT__TIL__1 d_inverter (rise_delay = 1n fall_delay = 1n)
.SUBCKT TIL_DRV__NON__1 1 2
* TIL Driver Model 1 = D/A input, 2 = out
aDACin1 [1] [2] aDAC
.MODEL aDAC dac_bridge (out_low= 0 out_high = 5 out_undef = 0)
.ENDS

.SUBCKT TIL_RCV__NON__1_Gate 1 2
* TIL Receiver Model 1 = input, 2 = A/D out
aADCin1 [1] [2] ADC
.MODEL ADC adc_bridge (in_low= {Vth} in_high = {Vth})
.ENDS

.SUBCKT TIL_RCV__NON__1 1 2
* TIL Receiver Model 1 = input, 2 = A/D out
aADCin1 [1] [2] ADC
.MODEL ADC adc_bridge (in_low= 2.5 in_high = 2.5)
.ENDS


.MODEL SR_LATCH__TIL__1 d_srlatch (sr_delay = 1n enable_delay = 1n
+ set_delay = 1n reset_delay= 1n
+ ic = 0 rise_delay = 1n fall_delay = 1n)

.ends

* SCR_A2 subcircuit
.subckt SCR_IDEAL_SCR_A2 Anode Cathode Gate PARAMS: Vth=2.5 Ih=0 Vfscr=0 Ron=1m Roff=1meg
E3 a2 0 Value = { if(I(vIscr)<=Ih,5,0) }

vIscr Anode 10 dc 0



xU6 8 cathode DIODE_IDEAL params: Vf={Vfscr} Rd={Ron/2} Rdoff={Roff/2}
.subckt DIODE_IDEAL a k params: Vf=0 Rd=1m Rdoff=1meg
ad1 %vd(a k) %id(a k) diode1
.model diode1 pwl(x_array=[{Vf-1} {Vf} {Vf+1}] y_array=[{-1/Rdoff} 0 {1/Rd}] fraction=false input_domain=0.0)
.ends


xS1 10 8 a3 0 VSwitchS1
.subckt VSwitchS1 1 2 3 4
S1 1 2 3 4 vsw0
.model vsw0 vswitch ( Roff={Roff/2} Ron={Ron/2} Voff=0 Von=1 )
.ends


aU5 7 d_constsource_U5
.model d_constsource_U5 d_constsource(state=1)


aU4 [a1 dU4.B dU4.C] reset AND2__TIL__1
xU4.B a2 dU4.B TIL_RCV__NON__1
xU4.C a3 dU4.C TIL_RCV__NON__1
aU3 dU3.A a1 NOT__TIL__1

xU3.A gate dU3.A TIL_RCV__NON__1_Gate

aU2 dU2.S reset 7
+ U2_OPEN_SET U2_OPEN_RESET
+ dU2.Q U2_OPEN_notQ SR_LATCH__TIL__1

xU2.S gate dU2.S TIL_RCV__NON__1_Gate


xU2.Q dU2.Q a3 TIL_DRV__NON__1



.MODEL AND2__TIL__1 d_and ( rise_delay = 1n fall_delay = 1n)
.MODEL NOT__TIL__1 d_inverter (rise_delay = 1n fall_delay = 1n)
.SUBCKT TIL_DRV__NON__1 1 2
* TIL Driver Model 1 = D/A input, 2 = out
aDACin1 [1] [2] aDAC
.MODEL aDAC dac_bridge (out_low= 0 out_high = 5 out_undef = 0)
.ENDS

.SUBCKT TIL_RCV__NON__1_Gate 1 2
* TIL Receiver Model 1 = input, 2 = A/D out
aADCin1 [1] [2] ADC
.MODEL ADC adc_bridge (in_low= {Vth} in_high = {Vth})
.ENDS

.SUBCKT TIL_RCV__NON__1 1 2
* TIL Receiver Model 1 = input, 2 = A/D out
aADCin1 [1] [2] ADC
.MODEL ADC adc_bridge (in_low= 2.5 in_high = 2.5)
.ENDS


.MODEL SR_LATCH__TIL__1 d_srlatch (sr_delay = 1n enable_delay = 1n
+ set_delay = 1n reset_delay= 1n
+ ic = 0 rise_delay = 1n fall_delay = 1n)

.ends

* SCR_A3 subcircuit
.subckt SCR_IDEAL_SCR_A3 Anode Cathode Gate PARAMS: Vth=2.5 Ih=0 Vfscr=0 Ron=1m Roff=1meg
E3 a2 0 Value = { if(I(vIscr)<=Ih,5,0) }

vIscr Anode 10 dc 0



xU6 8 cathode DIODE_IDEAL params: Vf={Vfscr} Rd={Ron/2} Rdoff={Roff/2}
.subckt DIODE_IDEAL a k params: Vf=0 Rd=1m Rdoff=1meg
ad1 %vd(a k) %id(a k) diode1
.model diode1 pwl(x_array=[{Vf-1} {Vf} {Vf+1}] y_array=[{-1/Rdoff} 0 {1/Rd}] fraction=false input_domain=0.0)
.ends


xS1 10 8 a3 0 VSwitchS1
.subckt VSwitchS1 1 2 3 4
S1 1 2 3 4 vsw0
.model vsw0 vswitch ( Roff={Roff/2} Ron={Ron/2} Voff=0 Von=1 )
.ends


aU5 7 d_constsource_U5
.model d_constsource_U5 d_constsource(state=1)


aU4 [a1 dU4.B dU4.C] reset AND2__TIL__1
xU4.B a2 dU4.B TIL_RCV__NON__1
xU4.C a3 dU4.C TIL_RCV__NON__1
aU3 dU3.A a1 NOT__TIL__1

xU3.A gate dU3.A TIL_RCV__NON__1_Gate

aU2 dU2.S reset 7
+ U2_OPEN_SET U2_OPEN_RESET
+ dU2.Q U2_OPEN_notQ SR_LATCH__TIL__1

xU2.S gate dU2.S TIL_RCV__NON__1_Gate


xU2.Q dU2.Q a3 TIL_DRV__NON__1



.MODEL AND2__TIL__1 d_and ( rise_delay = 1n fall_delay = 1n)
.MODEL NOT__TIL__1 d_inverter (rise_delay = 1n fall_delay = 1n)
.SUBCKT TIL_DRV__NON__1 1 2
* TIL Driver Model 1 = D/A input, 2 = out
aDACin1 [1] [2] aDAC
.MODEL aDAC dac_bridge (out_low= 0 out_high = 5 out_undef = 0)
.ENDS

.SUBCKT TIL_RCV__NON__1_Gate 1 2
* TIL Receiver Model 1 = input, 2 = A/D out
aADCin1 [1] [2] ADC
.MODEL ADC adc_bridge (in_low= {Vth} in_high = {Vth})
.ENDS

.SUBCKT TIL_RCV__NON__1 1 2
* TIL Receiver Model 1 = input, 2 = A/D out
aADCin1 [1] [2] ADC
.MODEL ADC adc_bridge (in_low= 2.5 in_high = 2.5)
.ENDS


.MODEL SR_LATCH__TIL__1 d_srlatch (sr_delay = 1n enable_delay = 1n
+ set_delay = 1n reset_delay= 1n
+ ic = 0 rise_delay = 1n fall_delay = 1n)

.ends

* U1 subcircuit
.subckt PHASEANGLE_FULL_U1 sync+ sync- alpha T1 T2 PARAMS: frequency=1 pulse_width=1 pulse_amplitude=1
AT1 %vd(sync+,sync-) alpha %vd(T1,0) alphamod


E1 alpha2 0 value={v(alpha)+180}
AT3 %vd(sync+,sync-) alpha2 %vd(T2,0) alphamod

.model alphamod phase_angle_controller(freq={frequency} pulse_width={pulse_width} pulse_amplitude={pulse_amplitude})
.ends
Errors and Warnings

Any error, warning or information messages appear below.
TypeDescription
A component update replaced the symbol for component SCR_A with a newer version. Check your schematic.
A component update replaced the symbol for component SCR_A1 with a newer version. Check your schematic.
A component update replaced the symbol for component SCR_A2 with a newer version. Check your schematic.
A component update replaced the symbol for component SCR_A3 with a newer version. Check your schematic.
Item
Document

Checkboxes toggle displayed values on and off.
Controlled Rectifier
Schematic

The simulation to run. See Simulation types for more information.

Name

Title of graph. Edit as desired.

End time

s

Time at which the simulation stops. Does not include pauses. Simulation does not occur in real time.
Start simulation

Mode
Threshold voltage levels.

Threshold voltage values used in the logic evaluation. See Digital Simulation for more information.

Output low

V
Output low voltage.

Maximum output voltage level to produce a low signal.

Input low threshold

V
Input low threshold voltage.

Maximum input voltage level for the signal to be considered low.

Input high threshold

V
Input high threshold voltage.

Minimum input voltage level for the signal to be considered high.

Output high

V
Output high voltage.

Minimum output voltage level to produce a high signal.

Width

Sheet width in grid squares.

Height

Sheet height in grid squares.

Grid

Toggles grid display.

Net Labels

Toggles all net labels.

Component Labels

Toggles all component labels.