*3.3.3 6 to 13 Up-Counter

Waiting for data

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ID:

x10

x0.1

Sheet:1

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SPICE

SPICE Netlist

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** 3.3.3 6 to 13 Up-Counter **
*
* Multisim Live SPICE netlist
*
*

* --- Circuit Topology ---

* Component: DG1
aDG1 bridgeDG1!OUT Digital_Source_DG1

xbridgeDG1!OUT bridgeDG1!OUT 1 REAL_CUSTOM_DAC PARAMS: lowV=0 maxLowV=0.8 unknownV=1 minHighV=2 highV=3.3 riseT=0 fallT=0

* Component: S1
xS1 0 2 1 SPDT_Switch_S1 Params: Ron=0.0001 Roff=100000000 State=1

* Component: U1
xU1 bridgeU1!A bridgeU1!B bridgeU1!C bridgeU1!D bridgeU1!UP bridgeU1!DOWN 10 bridgeU1!CLR 4 5 6 7 U1_NC_~BO U1_NC_~CO 74LS193_U1

xbridgeU1!A bridgeU1!A 0 REAL_CUSTOM_ADC PARAMS: lowV=0 maxLowV=0.8 unknownV=1 minHighV=2 highV=3.3 riseT=0 fallT=0

xbridgeU1!B bridgeU1!B 1 REAL_CUSTOM_ADC PARAMS: lowV=0 maxLowV=0.8 unknownV=1 minHighV=2 highV=3.3 riseT=0 fallT=0

xbridgeU1!C bridgeU1!C 1 REAL_CUSTOM_ADC PARAMS: lowV=0 maxLowV=0.8 unknownV=1 minHighV=2 highV=3.3 riseT=0 fallT=0

xbridgeU1!D bridgeU1!D 0 REAL_CUSTOM_ADC PARAMS: lowV=0 maxLowV=0.8 unknownV=1 minHighV=2 highV=3.3 riseT=0 fallT=0

xbridgeU1!UP bridgeU1!UP 11 REAL_CUSTOM_ADC PARAMS: lowV=0 maxLowV=0.8 unknownV=1 minHighV=2 highV=3.3 riseT=0 fallT=0

xbridgeU1!DOWN bridgeU1!DOWN 2 REAL_CUSTOM_ADC PARAMS: lowV=0 maxLowV=0.8 unknownV=1 minHighV=2 highV=3.3 riseT=0 fallT=0

xbridgeU1!CLR bridgeU1!CLR 0 REAL_CUSTOM_ADC PARAMS: lowV=0 maxLowV=0.8 unknownV=1 minHighV=2 highV=3.3 riseT=0 fallT=0

* Component: U2
aU2 [3 5 6 7] 10 Digital_NAND4_U2

* Component: U3
xU3 4 5 6 7 DIG_7SEG_HEX_U3

* Component: U4
aU4 4 3 Digital_Inverter_U4

* Component: V1
vV1 11 0
+ pulse( 0 5 0 1e-9 1e-9
+ { 50 * 0.01 / 40 }
+ { 1/40 } )

* --- Circuit Models ---

* DG1 model
.model Digital_Source_DG1 d_constsource(State=1)

* U2 model
.model Digital_NAND4_U2 d_nand (rise_delay=1e-9 fall_delay=1e-9)

* U4 model
.model Digital_Inverter_U4 d_inverter (rise_delay=1e-9 fall_delay=1e-9)

* --- Subcircuits ---

* S1 subcircuit
.subckt SPDT_Switch_S1 port1 port2 port3 Params: Ron=1e-8 Roff=1e30 State=0
V2 state 0 DC {State}
R1 state 6 10
V1 6 0 DC 0
W0 port2 port1 V1 NC_contact
W1 port2 port3 V1 NO_contact
.MODEL NO_contact ISWITCH (ION=0.05 IOFF=0.025 RON={Ron} ROFF={Roff})
.MODEL NC_contact ISWITCH (ION=0.05 IOFF=0.025 RON={Roff} ROFF={Ron})
.ends

* U1 subcircuit
**********************
*74LS193 SYNCHRONOUS 4-BIT UP/DOWN COUNTER (DUAL CLOCK WITH CLEAR)
***
.subckt 74LS193_U1 A B C D UP DOWN NLOAD CLR QA QB QC QD NBO NCO

ainv1 DOWN qinv1 inv
ainv2 UP qinv2 inv
ainv3 CLR qinv3 inv
ainv4 NLOAD qinv4 inv
ainv5 qnand1 s1 inv
ainv6 qnand3 s2 inv
ainv7 qnand5 s3 inv
ainv8 qnand7 s4 inv

abuff1 qinv2 buff1 up_co_buff
abuff2 qinv1 buff2 down_bo_buff
abuff4 qinv2 buff4 up_q_buff
abuff5 qinv1 buff5 down_q_buff
abuff6 qinv3 buff6 clr_q_buff

anand1 [A qinv4 qinv3] qnand1 nand
anand2 [buff2 nqa nqb nqc nqd] NBO nbo_nand
anand3 [QA QB QC QD buff1] NCO nco_nand
anand4 [qnand1 qinv4] qnand2 nand
anand5 [buff6 qnand2] r1 nand
anand6 [B qinv4 qinv3] qnand3 nand
anand7 [qnand3 qinv4] qnand4 nand
anand8 [buff6 qnand4] r2 nand
anand9 [C qinv4 qinv3] qnand5 nand
anand10 [qnand5 qinv4] qnand6 nand
anand11 [buff6 qnand6] r3 nand
anand12 [D qinv4 qinv3] qnand7 nand
anand13 [qnand7 qinv4] qnand8 nand
anand14 [buff6 qnand8] r4 nand

aand1 [buff5 nqa] qand1 and
aand2 [QA buff4] qand2 and
aand3 [buff5 nqa nqb] qand3 and
aand4 [QA QB buff4] qand4 and
aand5 [buff5 nqa nqb nqc] qand5 and
aand6 [QA QB QC buff4] qand6 and

anor1 [buff5 buff4] t1 nor
anor2 [qand1 qand2] t2 nor
anor3 [qand3 qand4] t3 nor
anor4 [qand5 qand6] t4 nor

ah hi high

ajkff1 hi hi t1 s1 r1 QA nqa jkff
ajkff2 hi hi t2 s2 r2 QB nqb jkff
ajkff3 hi hi t3 s3 r3 QC nqc jkff
ajkff4 hi hi t4 s4 r4 QD nqd jkff

.model jkff d_jkff (clk_delay=1e-9 set_delay=1e-9 reset_delay=1e-9 ic=0 rise_delay=1e-9 fall_delay=1e-9)

.model inv d_inverter
.model high d_pullup
.model nbo_nand d_nand
.model nco_nand d_nand
.model nand d_nand
.model and d_and
.model nor d_nor

.model up_co_buff d_buffer (rise_delay=26ns fall_delay=24ns)
.model down_bo_buff d_buffer (rise_delay=24ns fall_delay=24ns)
.model up_q_buff d_buffer (rise_delay=38ns fall_delay=47ns)
.model down_q_buff d_buffer (rise_delay=38ns fall_delay=47ns)
.model clr_q_buff d_buffer (fall_delay=35ns)

.ends

* U3 subcircuit
.subckt DIG_7SEG_HEX_U3 INA INB INC IND PARAMS: lowV=0 unknownV=1.0 highV=5.0 riseT=0 fallT=0

aU10 [IND 13 INB INA] 9 Digital_AND4
aU11 [14 15 16 17] U11_Y Digital_OR4
aU12 [10 INC 11 INA] 17 Digital_AND4
aU13 [IND INC 11 12] 16 Digital_AND4
aU14 [24 25 26 27] U14_Y Digital_OR4
aU15 [INC INB 12] 15 Digital_AND3
aU16 [1 2 3 34] U16_Y Digital_OR4
aU18 [10 13 INB 12] 20 Digital_AND4
aU19 [10 13 11 INA] 3 Digital_AND4
aU2 IND 10 Digital_Inverter
aU20 [IND INC 12] 18 Digital_AND3
aU21 [IND INC INB] 19 Digital_AND3
aU22 [10 INC 11 12] 2 Digital_AND4
aU23 [INC INB INA] 1 Digital_AND3
aU25 [4 22 23] U25_Y Digital_OR3
aU26 [10 INA] 4 Digital_AND2
aU27 [10 INC 11] 22 Digital_AND3
aU28 [13 11 INA] 23 Digital_AND3
aU29 [10 13 INA] 24 Digital_AND3
aU3 INC 13 Digital_Inverter
aU30 [10 13 INB] 25 Digital_AND3
aU31 [10 INB INA] 26 Digital_AND3
aU32 [IND 13 INB 12] 34 Digital_AND4
aU34 [29 28 30] U34_Y Digital_OR3
aU35 [10 13 11] 29 Digital_AND3
aU36 [IND INC 11 12] 28 Digital_AND4
aU37 [10 INC INB INA] 30 Digital_AND4
aU38 [IND INB INA] 14 Digital_AND3
aU39 [19 18 20] U39_Y Digital_OR3
aU4 INB 11 Digital_Inverter
aU40 [IND INC 11 INA] 27 Digital_AND4
aU5 INA 12 Digital_Inverter
aU6 [5 6 7 9] U6_Y Digital_OR4
aU7 [10 INC 11 12] 5 Digital_AND4
aU8 [10 13 11 INA] 6 Digital_AND4
aU9 [IND INC 11 INA] 7 Digital_AND4

vV1 8 0 dc {highV} ac 0 0
+ distof1 0 0
+ distof2 0 0

.model Digital_AND4 d_and (rise_delay=1e-9 fall_delay=1e-9)
.model Digital_OR4 d_or (rise_delay=1e-9 fall_delay=1e-9)
.model Digital_OR5 d_or (rise_delay=1e-9 fall_delay=1e-9)
.model Digital_AND3 d_and (rise_delay=1e-9 fall_delay=1e-9)
.model Digital_Inverter d_inverter (rise_delay=1e-9 fall_delay=1e-9)
.model Digital_OR3 d_or (rise_delay=1e-9 fall_delay=1e-9)
.model Digital_AND2 d_and (rise_delay=1e-9 fall_delay=1e-9)

xbridgeU11 U11_Y 32 AADAC
xbridgeU14 U14_Y 33 AADAC
xbridgeU16 U16_Y 36 AADAC
xbridgeU25 U25_Y 35 AADAC
xbridgeU34 U34_Y 37 AADAC
xbridgeU39 U39_Y 21 AADAC
xbridgeU6 U6_Y 31 AADAC

dd1 8 0vNode1 ledDiodeModel
Vsense1 0vNode1 31 DC 0
* Interactive sense node
b1 lit1 0 v = { if (i(Vsense1) < 0, 0, if( i(Vsense1) > 0.02, 1, { i(Vsense1) / 0.02 })) }

dd2 8 0vNode2 ledDiodeModel
Vsense2 0vNode2 32 DC 0
* Interactive sense node
b2 lit2 0 v = { if (i(Vsense2) < 0, 0, if( i(Vsense2) > 0.02, 1, { i(Vsense2) / 0.02 })) }

dd3 8 0vNode3 ledDiodeModel
Vsense3 0vNode3 21 DC 0
* Interactive sense node
b3 lit3 0 v = { if (i(Vsense3) < 0, 0, if( i(Vsense3) > 0.02, 1, { i(Vsense3) / 0.02 })) }

dd4 8 0vNode4 ledDiodeModel
Vsense4 0vNode4 36 DC 0
* Interactive sense node
b4 lit4 0 v = { if (i(Vsense4) < 0, 0, if( i(Vsense4) > 0.02, 1, { i(Vsense4) / 0.02 })) }

dd5 8 0vNode5 ledDiodeModel
Vsense5 0vNode5 35 DC 0
* Interactive sense node
b5 lit5 0 v = { if (i(Vsense5) < 0, 0, if( i(Vsense5) > 0.02, 1, { i(Vsense5) / 0.02 })) }

dd6 8 0vNode6 ledDiodeModel
Vsense6 0vNode6 33 DC 0
* Interactive sense node
b6 lit6 0 v = { if (i(Vsense6) < 0, 0, if( i(Vsense6) > 0.02, 1, { i(Vsense6) / 0.02 })) }

dd7 8 0vNode7 ledDiodeModel
Vsense7 0vNode7 37 DC 0
* Interactive sense node
b7 lit7 0 v = { if (i(Vsense7) < 0, 0, if( i(Vsense7) > 0.02, 1, { i(Vsense7) / 0.02 })) }

.model ledDiodeModel D( IS=1e-14 N=1 RS=0 IBV=1e-10 BV=1e+30 CJO=0 M=0.5 VJ=1 )

* --- Pin bridge models
.SUBCKT AADAC 1 2
* TIL Driver Model 1 = D/A input, 2 = out
aDACin1 [1] [2] aDAC
.MODEL aDAC dac_bridge (out_low = {lowV} out_high = {highV} out_undef = {unknownV} t_rise = {max(riseT,1e-9)} t_fall = {max(fallT,1e-9)})
.ENDS
.ENDS

* --- Pin bridge models

.SUBCKT REAL_CUSTOM_DAC 1 2 PARAMS: lowV=0 maxLowV=0.8 unknownV=1.0 minHighV=2.0 highV=5.0 riseT=0 fallT=0
* Ideal Driver Model 1 = A/D out, 2 = input
aDACin1 [1] [2] aDAC
.MODEL aDAC dac_bridge (out_low = {lowV} out_high = {highV} out_undef = {unknownV} t_rise = {max(riseT,1e-9)} t_fall = {max(fallT,1e-9)})
.ENDS

.SUBCKT REAL_CUSTOM_ADC 1 2 PARAMS: lowV=0 maxLowV=0.8 unknownV=1.0 minHighV=2.0 highV=5.0 riseT=0 fallT=0
* Ideal Receiver Model 1 = input, 2 = A/D out
aADCin1 [2] [1] ADC
.MODEL ADC adc_bridge (in_low = {maxLowV} in_high = {minHighV})
.ENDS

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Item

Document

Section

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Type

Rise time

Time it takes for signal to transition from low to high.

With non-zero rise time, the signal converts to an analog signal from a digital signal.

Fall time

Time it takes for signal to transition from high to low.

With non-zero fall time, the signal converts to an analog signal from a digital signal.

Use document settings

Use logic levels settings from Document tab.

Threshold voltage levels.

Threshold voltage values used in the logic evaluation. See Digital Simulation for more information.

Output low

Output low voltage.

Maximum output voltage level to produce a low signal.

Input low threshold

Input low threshold voltage.

Maximum input voltage level for the signal to be considered low.

Input high threshold

Input high threshold voltage.

Minimum input voltage level for the signal to be considered high.

Output high

Output high voltage.

Minimum output voltage level to produce a high signal.

Type Probe

Select desired function.

Function

Use document settings

Use logic levels settings from Document tab.

Threshold voltage levels.

Threshold voltage values used in the logic evaluation. See Digital Simulation for more information.

Output low

Output low voltage.

Maximum output voltage level to produce a low signal.

Input low threshold

Input low threshold voltage.

Maximum input voltage level for the signal to be considered low.

Input high threshold

Input high threshold voltage.

Minimum input voltage level for the signal to be considered high.

Output high

Output high voltage.

Minimum output voltage level to produce a high signal.

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Displays periodic measurements on probe during Interactive simulation.

Bias point(s)

Displays bias points on probe for DC Op simulation.

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Name 3.3.3 6 to 13 Up-Counter

Type Schematic

The simulation to run. See Simulation types for more information.

Name

Title of graph. Edit as desired.

End time

Time at which the simulation stops. Does not include pauses. Simulation does not occur in real time.

Start simulation

RELTOL

Relative error tolerance. A simulation wide accuracy control used to establish convergence.

VNTOL

Absolute voltage error tolerance. Defines the minimum value for voltage where it may still be considered accurate.

ABSTOL

Absolute current error tolerance. Defines the minimum value for current where it may still be considered accurate.

ITL1

DC iteration limit. Number of iterative passes done on DC circuit equations in attempt to reach convergence in simulation.

ITL4

Upper iteration limit. Number of iterative passes done per time point, on Transient circuit equations in attempt to reach convergence in simulation.

Integration method. The numerical integration method used in transient analysis.

Temp

℃

Operating temperature. The temperature at which the entire circuit will be simulated.

Insert shunt resistance

Inserts a resistance of RSHUNT from every analog node to ground. Will aid in convergence, but alter the behavior of the circuit.

RSHUNT

Shunt resistance. This eliminates singular matrix errors that result from a lack of a DC path to ground.

Reset to default

Threshold voltage levels.

Threshold voltage values used in the logic evaluation. See Digital Simulation for more information.

Output low

Output low voltage.

Maximum output voltage level to produce a low signal.

Input low threshold

Input low threshold voltage.

Maximum input voltage level for the signal to be considered low.

Input high threshold

Input high threshold voltage.

Minimum input voltage level for the signal to be considered high.

Output high

Output high voltage.

Minimum output voltage level to produce a high signal.

Width

Sheet width in grid squares.

Height

Sheet height in grid squares.

Grid

Toggles grid display.

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3.3.3 6 to 13 Up-Counter