*AidenPyle2.1.6 Unsimplified

Waiting for data

Signal	Value
Signal	Value

Cursor 1	Cursor 2	∆X	1/∆X	∆Y	∆Y (Phase)

Out of date
V	—
V	—
V_PP	—
V_RMS	—
V_AV	—
f_V	—
I	—
I	—
I_PP	—
I_RMS	—
I_AV	—
f_I	—
D	—

ID:

x10

x0.1

Sheet:1

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SPICE

SPICE Netlist

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** AidenPyle2.1.6 Unsimplified **
*
* Multisim Live SPICE netlist
*
*

* --- Circuit Topology ---

* Component: DG1
aDG1 bridgeDG1!OUT Digital_Source_DG1

xbridgeDG1!OUT bridgeDG1!OUT 1 REAL_CUSTOM_DAC PARAMS: lowV=0 maxLowV=0.8 unknownV=1 minHighV=2 highV=3.3 riseT=0 fallT=0

* Component: P
xP 1 2 0 SPDT_Switch_P Params: Ron=0.0001 Roff=100000000 State=0

* Component: S
xS 1 4 0 SPDT_Switch_S Params: Ron=0.0001 Roff=100000000 State=0

* Component: T
xT 1 5 0 SPDT_Switch_T Params: Ron=0.0001 Roff=100000000 State=0

* Component: U1
aU1 bridgeU1!A 6 Digital_Inverter_U1

xbridgeU1!A bridgeU1!A 2 REAL_CUSTOM_ADC PARAMS: lowV=0 maxLowV=0.8 unknownV=1 minHighV=2 highV=3.3 riseT=0 fallT=0

* Component: U10
aU10 [13 bridgeU10!B] 27 Digital_AND2_U10

xbridgeU10!B bridgeU10!B 5 REAL_CUSTOM_ADC PARAMS: lowV=0 maxLowV=0.8 unknownV=1 minHighV=2 highV=3.3 riseT=0 fallT=0

* Component: U11
aU11 [bridgeU11!A 7] 14 Digital_AND2_U11

xbridgeU11!A bridgeU11!A 2 REAL_CUSTOM_ADC PARAMS: lowV=0 maxLowV=0.8 unknownV=1 minHighV=2 highV=3.3 riseT=0 fallT=0

* Component: U12
aU12 [14 bridgeU12!B] 15 Digital_AND2_U12

xbridgeU12!B bridgeU12!B 4 REAL_CUSTOM_ADC PARAMS: lowV=0 maxLowV=0.8 unknownV=1 minHighV=2 highV=3.3 riseT=0 fallT=0

* Component: U13
aU13 [15 9] 28 Digital_AND2_U13

* Component: U14
aU14 [bridgeU14!A 7] 16 Digital_AND2_U14

xbridgeU14!A bridgeU14!A 2 REAL_CUSTOM_ADC PARAMS: lowV=0 maxLowV=0.8 unknownV=1 minHighV=2 highV=3.3 riseT=0 fallT=0

* Component: U15
aU15 [16 bridgeU15!B] 17 Digital_AND2_U15

xbridgeU15!B bridgeU15!B 4 REAL_CUSTOM_ADC PARAMS: lowV=0 maxLowV=0.8 unknownV=1 minHighV=2 highV=3.3 riseT=0 fallT=0

* Component: U16
aU16 [17 bridgeU16!B] 29 Digital_AND2_U16

xbridgeU16!B bridgeU16!B 5 REAL_CUSTOM_ADC PARAMS: lowV=0 maxLowV=0.8 unknownV=1 minHighV=2 highV=3.3 riseT=0 fallT=0

* Component: U17
aU17 [bridgeU17!A bridgeU17!B] 18 Digital_AND2_U17

xbridgeU17!A bridgeU17!A 2 REAL_CUSTOM_ADC PARAMS: lowV=0 maxLowV=0.8 unknownV=1 minHighV=2 highV=3.3 riseT=0 fallT=0

xbridgeU17!B bridgeU17!B 3 REAL_CUSTOM_ADC PARAMS: lowV=0 maxLowV=0.8 unknownV=1 minHighV=2 highV=3.3 riseT=0 fallT=0

* Component: U18
aU18 [18 8] 19 Digital_AND2_U18

* Component: U19
aU19 [19 9] 30 Digital_AND2_U19

* Component: U2
aU2 bridgeU2!A 7 Digital_Inverter_U2

xbridgeU2!A bridgeU2!A 3 REAL_CUSTOM_ADC PARAMS: lowV=0 maxLowV=0.8 unknownV=1 minHighV=2 highV=3.3 riseT=0 fallT=0

* Component: U20
aU20 [bridgeU20!A bridgeU20!B] 20 Digital_AND2_U20

xbridgeU20!A bridgeU20!A 2 REAL_CUSTOM_ADC PARAMS: lowV=0 maxLowV=0.8 unknownV=1 minHighV=2 highV=3.3 riseT=0 fallT=0

xbridgeU20!B bridgeU20!B 3 REAL_CUSTOM_ADC PARAMS: lowV=0 maxLowV=0.8 unknownV=1 minHighV=2 highV=3.3 riseT=0 fallT=0

* Component: U21
aU21 [20 8] 21 Digital_AND2_U21

* Component: U22
aU22 [21 bridgeU22!B] 31 Digital_AND2_U22

xbridgeU22!B bridgeU22!B 5 REAL_CUSTOM_ADC PARAMS: lowV=0 maxLowV=0.8 unknownV=1 minHighV=2 highV=3.3 riseT=0 fallT=0

* Component: U23
aU23 [bridgeU23!A bridgeU23!B] 22 Digital_AND2_U23

xbridgeU23!A bridgeU23!A 2 REAL_CUSTOM_ADC PARAMS: lowV=0 maxLowV=0.8 unknownV=1 minHighV=2 highV=3.3 riseT=0 fallT=0

xbridgeU23!B bridgeU23!B 3 REAL_CUSTOM_ADC PARAMS: lowV=0 maxLowV=0.8 unknownV=1 minHighV=2 highV=3.3 riseT=0 fallT=0

* Component: U24
aU24 [22 bridgeU24!B] 23 Digital_AND2_U24

xbridgeU24!B bridgeU24!B 4 REAL_CUSTOM_ADC PARAMS: lowV=0 maxLowV=0.8 unknownV=1 minHighV=2 highV=3.3 riseT=0 fallT=0

* Component: U25
aU25 [23 9] 32 Digital_AND2_U25

* Component: U26
aU26 [bridgeU26!A bridgeU26!B] 24 Digital_AND2_U26

xbridgeU26!A bridgeU26!A 2 REAL_CUSTOM_ADC PARAMS: lowV=0 maxLowV=0.8 unknownV=1 minHighV=2 highV=3.3 riseT=0 fallT=0

xbridgeU26!B bridgeU26!B 3 REAL_CUSTOM_ADC PARAMS: lowV=0 maxLowV=0.8 unknownV=1 minHighV=2 highV=3.3 riseT=0 fallT=0

* Component: U27
aU27 [24 bridgeU27!B] 25 Digital_AND2_U27

xbridgeU27!B bridgeU27!B 4 REAL_CUSTOM_ADC PARAMS: lowV=0 maxLowV=0.8 unknownV=1 minHighV=2 highV=3.3 riseT=0 fallT=0

* Component: U28
aU28 [25 bridgeU28!B] 33 Digital_AND2_U28

xbridgeU28!B bridgeU28!B 5 REAL_CUSTOM_ADC PARAMS: lowV=0 maxLowV=0.8 unknownV=1 minHighV=2 highV=3.3 riseT=0 fallT=0

* Component: U29
aU29 [26 27] 34 Digital_OR2_U29

* Component: U3
aU3 bridgeU3!A 8 Digital_Inverter_U3

xbridgeU3!A bridgeU3!A 4 REAL_CUSTOM_ADC PARAMS: lowV=0 maxLowV=0.8 unknownV=1 minHighV=2 highV=3.3 riseT=0 fallT=0

* Component: U30
aU30 [28 29] 35 Digital_OR2_U30

* Component: U31
aU31 [30 31] 36 Digital_OR2_U31

* Component: U32
aU32 [32 33] 37 Digital_OR2_U32

* Component: U33
aU33 [36 37] 39 Digital_OR2_U33

* Component: U34
aU34 [34 35] 38 Digital_OR2_U34

* Component: U35
aU35 [38 39] 40 Digital_OR2_U35

* Component: U4
aU4 bridgeU4!A 9 Digital_Inverter_U4

xbridgeU4!A bridgeU4!A 5 REAL_CUSTOM_ADC PARAMS: lowV=0 maxLowV=0.8 unknownV=1 minHighV=2 highV=3.3 riseT=0 fallT=0

* Component: U5
aU5 [6 bridgeU5!B] 10 Digital_AND2_U5

xbridgeU5!B bridgeU5!B 3 REAL_CUSTOM_ADC PARAMS: lowV=0 maxLowV=0.8 unknownV=1 minHighV=2 highV=3.3 riseT=0 fallT=0

* Component: U6
aU6 [10 bridgeU6!B] 11 Digital_AND2_U6

xbridgeU6!B bridgeU6!B 4 REAL_CUSTOM_ADC PARAMS: lowV=0 maxLowV=0.8 unknownV=1 minHighV=2 highV=3.3 riseT=0 fallT=0

* Component: U7
aU7 [11 bridgeU7!B] 26 Digital_AND2_U7

xbridgeU7!B bridgeU7!B 5 REAL_CUSTOM_ADC PARAMS: lowV=0 maxLowV=0.8 unknownV=1 minHighV=2 highV=3.3 riseT=0 fallT=0

* Component: U8
aU8 [bridgeU8!A 7] 12 Digital_AND2_U8

xbridgeU8!A bridgeU8!A 2 REAL_CUSTOM_ADC PARAMS: lowV=0 maxLowV=0.8 unknownV=1 minHighV=2 highV=3.3 riseT=0 fallT=0

* Component: U9
aU9 [12 8] 13 Digital_AND2_U9

* Component: V
xV 1 3 0 SPDT_Switch_V Params: Ron=0.0001 Roff=100000000 State=0

* --- Circuit Models ---

* DG1 model
.model Digital_Source_DG1 d_constsource(State=1)

* U1 model
.model Digital_Inverter_U1 d_inverter (rise_delay=1e-9 fall_delay=1e-9)

* U10 model
.model Digital_AND2_U10 d_and (rise_delay=1e-9 fall_delay=1e-9)

* U11 model
.model Digital_AND2_U11 d_and (rise_delay=1e-9 fall_delay=1e-9)

* U12 model
.model Digital_AND2_U12 d_and (rise_delay=1e-9 fall_delay=1e-9)

* U13 model
.model Digital_AND2_U13 d_and (rise_delay=1e-9 fall_delay=1e-9)

* U14 model
.model Digital_AND2_U14 d_and (rise_delay=1e-9 fall_delay=1e-9)

* U15 model
.model Digital_AND2_U15 d_and (rise_delay=1e-9 fall_delay=1e-9)

* U16 model
.model Digital_AND2_U16 d_and (rise_delay=1e-9 fall_delay=1e-9)

* U17 model
.model Digital_AND2_U17 d_and (rise_delay=1e-9 fall_delay=1e-9)

* U18 model
.model Digital_AND2_U18 d_and (rise_delay=1e-9 fall_delay=1e-9)

* U19 model
.model Digital_AND2_U19 d_and (rise_delay=1e-9 fall_delay=1e-9)

* U2 model
.model Digital_Inverter_U2 d_inverter (rise_delay=1e-9 fall_delay=1e-9)

* U20 model
.model Digital_AND2_U20 d_and (rise_delay=1e-9 fall_delay=1e-9)

* U21 model
.model Digital_AND2_U21 d_and (rise_delay=1e-9 fall_delay=1e-9)

* U22 model
.model Digital_AND2_U22 d_and (rise_delay=1e-9 fall_delay=1e-9)

* U23 model
.model Digital_AND2_U23 d_and (rise_delay=1e-9 fall_delay=1e-9)

* U24 model
.model Digital_AND2_U24 d_and (rise_delay=1e-9 fall_delay=1e-9)

* U25 model
.model Digital_AND2_U25 d_and (rise_delay=1e-9 fall_delay=1e-9)

* U26 model
.model Digital_AND2_U26 d_and (rise_delay=1e-9 fall_delay=1e-9)

* U27 model
.model Digital_AND2_U27 d_and (rise_delay=1e-9 fall_delay=1e-9)

* U28 model
.model Digital_AND2_U28 d_and (rise_delay=1e-9 fall_delay=1e-9)

* U29 model
.model Digital_OR2_U29 d_or (rise_delay=1e-9 fall_delay=1e-9)

* U3 model
.model Digital_Inverter_U3 d_inverter (rise_delay=1e-9 fall_delay=1e-9)

* U30 model
.model Digital_OR2_U30 d_or (rise_delay=1e-9 fall_delay=1e-9)

* U31 model
.model Digital_OR2_U31 d_or (rise_delay=1e-9 fall_delay=1e-9)

* U32 model
.model Digital_OR2_U32 d_or (rise_delay=1e-9 fall_delay=1e-9)

* U33 model
.model Digital_OR2_U33 d_or (rise_delay=1e-9 fall_delay=1e-9)

* U34 model
.model Digital_OR2_U34 d_or (rise_delay=1e-9 fall_delay=1e-9)

* U35 model
.model Digital_OR2_U35 d_or (rise_delay=1e-9 fall_delay=1e-9)

* U4 model
.model Digital_Inverter_U4 d_inverter (rise_delay=1e-9 fall_delay=1e-9)

* U5 model
.model Digital_AND2_U5 d_and (rise_delay=1e-9 fall_delay=1e-9)

* U6 model
.model Digital_AND2_U6 d_and (rise_delay=1e-9 fall_delay=1e-9)

* U7 model
.model Digital_AND2_U7 d_and (rise_delay=1e-9 fall_delay=1e-9)

* U8 model
.model Digital_AND2_U8 d_and (rise_delay=1e-9 fall_delay=1e-9)

* U9 model
.model Digital_AND2_U9 d_and (rise_delay=1e-9 fall_delay=1e-9)

* --- Subcircuits ---

* P subcircuit
.subckt SPDT_Switch_P port1 port2 port3 Params: Ron=1e-8 Roff=1e30 State=0
V2 state 0 DC {State}
R1 state 6 10
V1 6 0 DC 0
W0 port2 port1 V1 NC_contact
W1 port2 port3 V1 NO_contact
.MODEL NO_contact ISWITCH (ION=0.05 IOFF=0.025 RON={Ron} ROFF={Roff})
.MODEL NC_contact ISWITCH (ION=0.05 IOFF=0.025 RON={Roff} ROFF={Ron})
.ends

* S subcircuit
.subckt SPDT_Switch_S port1 port2 port3 Params: Ron=1e-8 Roff=1e30 State=0
V2 state 0 DC {State}
R1 state 6 10
V1 6 0 DC 0
W0 port2 port1 V1 NC_contact
W1 port2 port3 V1 NO_contact
.MODEL NO_contact ISWITCH (ION=0.05 IOFF=0.025 RON={Ron} ROFF={Roff})
.MODEL NC_contact ISWITCH (ION=0.05 IOFF=0.025 RON={Roff} ROFF={Ron})
.ends

* T subcircuit
.subckt SPDT_Switch_T port1 port2 port3 Params: Ron=1e-8 Roff=1e30 State=0
V2 state 0 DC {State}
R1 state 6 10
V1 6 0 DC 0
W0 port2 port1 V1 NC_contact
W1 port2 port3 V1 NO_contact
.MODEL NO_contact ISWITCH (ION=0.05 IOFF=0.025 RON={Ron} ROFF={Roff})
.MODEL NC_contact ISWITCH (ION=0.05 IOFF=0.025 RON={Roff} ROFF={Ron})
.ends

* V subcircuit
.subckt SPDT_Switch_V port1 port2 port3 Params: Ron=1e-8 Roff=1e30 State=0
V2 state 0 DC {State}
R1 state 6 10
V1 6 0 DC 0
W0 port2 port1 V1 NC_contact
W1 port2 port3 V1 NO_contact
.MODEL NO_contact ISWITCH (ION=0.05 IOFF=0.025 RON={Ron} ROFF={Roff})
.MODEL NC_contact ISWITCH (ION=0.05 IOFF=0.025 RON={Roff} ROFF={Ron})
.ends

* --- Pin bridge models

.SUBCKT REAL_CUSTOM_DAC 1 2 PARAMS: lowV=0 maxLowV=0.8 unknownV=1.0 minHighV=2.0 highV=5.0 riseT=0 fallT=0
* Ideal Driver Model 1 = A/D out, 2 = input
aDACin1 [1] [2] aDAC
.MODEL aDAC dac_bridge (out_low = {lowV} out_high = {highV} out_undef = {unknownV} t_rise = {max(riseT,1e-9)} t_fall = {max(fallT,1e-9)})
.ENDS

.SUBCKT REAL_CUSTOM_ADC 1 2 PARAMS: lowV=0 maxLowV=0.8 unknownV=1.0 minHighV=2.0 highV=5.0 riseT=0 fallT=0
* Ideal Receiver Model 1 = input, 2 = A/D out
aADCin1 [2] [1] ADC
.MODEL ADC adc_bridge (in_low = {maxLowV} in_high = {minHighV})
.ENDS

Errors and Warnings

Any error, warning or information messages appear below.

Item

Document

Section

Only one section is available for multisection components.

Type

Rise time

Time it takes for signal to transition from low to high.

With non-zero rise time, the signal converts to an analog signal from a digital signal.

Fall time

Time it takes for signal to transition from high to low.

With non-zero fall time, the signal converts to an analog signal from a digital signal.

Use document settings

Use logic levels settings from Document tab.

Threshold voltage levels.

Threshold voltage values used in the logic evaluation. See Digital Simulation for more information.

Output low

Output low voltage.

Maximum output voltage level to produce a low signal.

Input low threshold

Input low threshold voltage.

Maximum input voltage level for the signal to be considered low.

Input high threshold

Input high threshold voltage.

Minimum input voltage level for the signal to be considered high.

Output high

Output high voltage.

Minimum output voltage level to produce a high signal.

Type Probe

Select desired function.

Function

Use document settings

Use logic levels settings from Document tab.

Threshold voltage levels.

Threshold voltage values used in the logic evaluation. See Digital Simulation for more information.

Output low

Output low voltage.

Maximum output voltage level to produce a low signal.

Input low threshold

Input low threshold voltage.

Maximum input voltage level for the signal to be considered low.

Input high threshold

Input high threshold voltage.

Minimum input voltage level for the signal to be considered high.

Output high

Output high voltage.

Minimum output voltage level to produce a high signal.

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Available functions, constants and operators for the expression.

Source

Data origin.

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Web address of the selected Source.

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Connect

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Connecting

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Switch on to stream data from Source when simulation runs.

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Source type

Application used to generate the Source data.

Data type

Type of simulation data in Source.

File size

Size of the referenced file. Total file size for all data plotters cannot exceed 100 MB.

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Data streaming is only available in interactive simulation

Instantaneous

Displays instantaneous measurements on probe during interactive simulation.

Periodic

Displays periodic measurements on probe during Interactive simulation.

Bias point(s)

Displays bias points on probe for DC Op simulation.

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Name AidenPyle2.1.6 Unsimplified

Type Schematic

The simulation to run. See Simulation types for more information.

Name

Title of graph. Edit as desired.

End time

Time at which the simulation stops. Does not include pauses. Simulation does not occur in real time.

Start simulation

RELTOL

Relative error tolerance. A simulation wide accuracy control used to establish convergence.

VNTOL

Absolute voltage error tolerance. Defines the minimum value for voltage where it may still be considered accurate.

ABSTOL

Absolute current error tolerance. Defines the minimum value for current where it may still be considered accurate.

ITL1

DC iteration limit. Number of iterative passes done on DC circuit equations in attempt to reach convergence in simulation.

ITL4

Upper iteration limit. Number of iterative passes done per time point, on Transient circuit equations in attempt to reach convergence in simulation.

Integration method. The numerical integration method used in transient analysis.

Temp

℃

Operating temperature. The temperature at which the entire circuit will be simulated.

Insert shunt resistance

Inserts a resistance of RSHUNT from every analog node to ground. Will aid in convergence, but alter the behavior of the circuit.

RSHUNT

Shunt resistance. This eliminates singular matrix errors that result from a lack of a DC path to ground.

Reset to default

Threshold voltage levels.

Threshold voltage values used in the logic evaluation. See Digital Simulation for more information.

Output low

Output low voltage.

Maximum output voltage level to produce a low signal.

Input low threshold

Input low threshold voltage.

Maximum input voltage level for the signal to be considered low.

Input high threshold

Input high threshold voltage.

Minimum input voltage level for the signal to be considered high.

Output high

Output high voltage.

Minimum output voltage level to produce a high signal.

Width

Sheet width in grid squares.

Height

Sheet height in grid squares.

Grid

Toggles grid display.

Net Labels

Toggles all net labels.

Component Labels

Toggles all component labels.

AidenPyle2.1.6 Unsimplified