*Omi Nikolai 4 bit Binary Up Counter

Waiting for data

Signal	Value
Signal	Value

Cursor 1	Cursor 2	∆X	1/∆X	∆Y	∆Y (Phase)

Out of date
V	—
V	—
V_PP	—
V_RMS	—
V_AV	—
f_V	—
I	—
I	—
I_PP	—
I_RMS	—
I_AV	—
f_I	—
D	—

Out of date
V	—
V	—
V_PP	—
V_RMS	—
V_AV	—
f_V	—
I	—
I	—
I_PP	—
I_RMS	—
I_AV	—
f_I	—
D	—

Out of date
V	—
V	—
V_PP	—
V_RMS	—
V_AV	—
f_V	—
I	—
I	—
I_PP	—
I_RMS	—
I_AV	—
f_I	—
D	—

ID:

x10

x0.1

Sheet:1

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SPICE

SPICE Netlist

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** Omi Nikolai 4 bit Binary Up Counter **
*
* Multisim Live SPICE netlist
*
*

* --- Circuit Topology ---

* Component: Clear
xClear 0 1 7 SPDT_Switch_Clear Params: Ron=0.0001 Roff=100000000 State=1

* Component: DG1
aDG1 bridgeDG1!OUT Digital_Source_DG1

xbridgeDG1!OUT bridgeDG1!OUT 7 REAL_CUSTOM_DAC PARAMS: lowV=0 maxLowV=0.8 unknownV=1 minHighV=2 highV=3.3 riseT=0 fallT=0

* Component: Hex_Display
xHex_Display 3 6 9 bridgeHex_Display!1 DIG_7SEG_HEX_Hex_Display

xbridgeHex_Display!1 bridgeHex_Display!1 0 REAL_CUSTOM_ADC PARAMS: lowV=0 maxLowV=0.8 unknownV=1 minHighV=2 highV=3.3 riseT=0 fallT=0

* Component: JK0
xJK0 bridgeJK0!J bridgeJK0!K bridgeJK0!CLK bridgeJK0!SET bridgeJK0!RESET 3 JK0_NC_~Q Digital_JKFlipFlop_JK0 PARAMS: Negative_Edge_Clock=1 Negative_SET_RESET=1 Rise_delay=1e-9 Fall_delay=1e-9 Clk_delay=1e-9 Set_delay=1e-9 Reset_delay=1e-9 Ic=0

xbridgeJK0!J bridgeJK0!J 7 REAL_CUSTOM_ADC PARAMS: lowV=0 maxLowV=0.8 unknownV=1 minHighV=2 highV=3.3 riseT=0 fallT=0

xbridgeJK0!K bridgeJK0!K 7 REAL_CUSTOM_ADC PARAMS: lowV=0 maxLowV=0.8 unknownV=1 minHighV=2 highV=3.3 riseT=0 fallT=0

xbridgeJK0!CLK bridgeJK0!CLK 2 REAL_CUSTOM_ADC PARAMS: lowV=0 maxLowV=0.8 unknownV=1 minHighV=2 highV=3.3 riseT=0 fallT=0

xbridgeJK0!SET bridgeJK0!SET 7 REAL_CUSTOM_ADC PARAMS: lowV=0 maxLowV=0.8 unknownV=1 minHighV=2 highV=3.3 riseT=0 fallT=0

xbridgeJK0!RESET bridgeJK0!RESET 1 REAL_CUSTOM_ADC PARAMS: lowV=0 maxLowV=0.8 unknownV=1 minHighV=2 highV=3.3 riseT=0 fallT=0

* Component: JK1
xJK1 bridgeJK1!J bridgeJK1!K 3 bridgeJK1!SET bridgeJK1!RESET 6 JK1_NC_~Q Digital_JKFlipFlop_JK1 PARAMS: Negative_Edge_Clock=1 Negative_SET_RESET=1 Rise_delay=1e-9 Fall_delay=1e-9 Clk_delay=1e-9 Set_delay=1e-9 Reset_delay=1e-9 Ic=0

xbridgeJK1!J bridgeJK1!J 7 REAL_CUSTOM_ADC PARAMS: lowV=0 maxLowV=0.8 unknownV=1 minHighV=2 highV=3.3 riseT=0 fallT=0

xbridgeJK1!K bridgeJK1!K 7 REAL_CUSTOM_ADC PARAMS: lowV=0 maxLowV=0.8 unknownV=1 minHighV=2 highV=3.3 riseT=0 fallT=0

xbridgeJK1!SET bridgeJK1!SET 7 REAL_CUSTOM_ADC PARAMS: lowV=0 maxLowV=0.8 unknownV=1 minHighV=2 highV=3.3 riseT=0 fallT=0

xbridgeJK1!RESET bridgeJK1!RESET 1 REAL_CUSTOM_ADC PARAMS: lowV=0 maxLowV=0.8 unknownV=1 minHighV=2 highV=3.3 riseT=0 fallT=0

* Component: JK2
xJK2 bridgeJK2!J bridgeJK2!K 6 bridgeJK2!SET bridgeJK2!RESET 9 JK2_NC_~Q Digital_JKFlipFlop_JK2 PARAMS: Negative_Edge_Clock=1 Negative_SET_RESET=1 Rise_delay=1e-9 Fall_delay=1e-9 Clk_delay=1e-9 Set_delay=1e-9 Reset_delay=1e-9 Ic=0

xbridgeJK2!J bridgeJK2!J 7 REAL_CUSTOM_ADC PARAMS: lowV=0 maxLowV=0.8 unknownV=1 minHighV=2 highV=3.3 riseT=0 fallT=0

xbridgeJK2!K bridgeJK2!K 7 REAL_CUSTOM_ADC PARAMS: lowV=0 maxLowV=0.8 unknownV=1 minHighV=2 highV=3.3 riseT=0 fallT=0

xbridgeJK2!SET bridgeJK2!SET 7 REAL_CUSTOM_ADC PARAMS: lowV=0 maxLowV=0.8 unknownV=1 minHighV=2 highV=3.3 riseT=0 fallT=0

xbridgeJK2!RESET bridgeJK2!RESET 1 REAL_CUSTOM_ADC PARAMS: lowV=0 maxLowV=0.8 unknownV=1 minHighV=2 highV=3.3 riseT=0 fallT=0

* Component: V1
vV1 2 0
+ pulse( 0 5 0 1e-9 1e-9
+ { 50 * 0.01 / 100 }
+ { 1/100 } )

* --- Circuit Models ---

* DG1 model
.model Digital_Source_DG1 d_constsource(State=1)

* --- Subcircuits ---

* Clear subcircuit
.subckt SPDT_Switch_Clear port1 port2 port3 Params: Ron=1e-8 Roff=1e30 State=0
V2 state 0 DC {State}
R1 state 6 10
V1 6 0 DC 0
W0 port2 port1 V1 NC_contact
W1 port2 port3 V1 NO_contact
.MODEL NO_contact ISWITCH (ION=0.05 IOFF=0.025 RON={Ron} ROFF={Roff})
.MODEL NC_contact ISWITCH (ION=0.05 IOFF=0.025 RON={Roff} ROFF={Ron})
.ends

* Hex_Display subcircuit
.subckt DIG_7SEG_HEX_Hex_Display INA INB INC IND PARAMS: lowV=0 unknownV=1.0 highV=5.0 riseT=0 fallT=0

aU10 [IND 13 INB INA] 9 Digital_AND4
aU11 [14 15 16 17] U11_Y Digital_OR4
aU12 [10 INC 11 INA] 17 Digital_AND4
aU13 [IND INC 11 12] 16 Digital_AND4
aU14 [24 25 26 27] U14_Y Digital_OR4
aU15 [INC INB 12] 15 Digital_AND3
aU16 [1 2 3 34] U16_Y Digital_OR4
aU18 [10 13 INB 12] 20 Digital_AND4
aU19 [10 13 11 INA] 3 Digital_AND4
aU2 IND 10 Digital_Inverter
aU20 [IND INC 12] 18 Digital_AND3
aU21 [IND INC INB] 19 Digital_AND3
aU22 [10 INC 11 12] 2 Digital_AND4
aU23 [INC INB INA] 1 Digital_AND3
aU25 [4 22 23] U25_Y Digital_OR3
aU26 [10 INA] 4 Digital_AND2
aU27 [10 INC 11] 22 Digital_AND3
aU28 [13 11 INA] 23 Digital_AND3
aU29 [10 13 INA] 24 Digital_AND3
aU3 INC 13 Digital_Inverter
aU30 [10 13 INB] 25 Digital_AND3
aU31 [10 INB INA] 26 Digital_AND3
aU32 [IND 13 INB 12] 34 Digital_AND4
aU34 [29 28 30] U34_Y Digital_OR3
aU35 [10 13 11] 29 Digital_AND3
aU36 [IND INC 11 12] 28 Digital_AND4
aU37 [10 INC INB INA] 30 Digital_AND4
aU38 [IND INB INA] 14 Digital_AND3
aU39 [19 18 20] U39_Y Digital_OR3
aU4 INB 11 Digital_Inverter
aU40 [IND INC 11 INA] 27 Digital_AND4
aU5 INA 12 Digital_Inverter
aU6 [5 6 7 9] U6_Y Digital_OR4
aU7 [10 INC 11 12] 5 Digital_AND4
aU8 [10 13 11 INA] 6 Digital_AND4
aU9 [IND INC 11 INA] 7 Digital_AND4

vV1 8 0 dc {highV} ac 0 0
+ distof1 0 0
+ distof2 0 0

.model Digital_AND4 d_and (rise_delay=1e-9 fall_delay=1e-9)
.model Digital_OR4 d_or (rise_delay=1e-9 fall_delay=1e-9)
.model Digital_OR5 d_or (rise_delay=1e-9 fall_delay=1e-9)
.model Digital_AND3 d_and (rise_delay=1e-9 fall_delay=1e-9)
.model Digital_Inverter d_inverter (rise_delay=1e-9 fall_delay=1e-9)
.model Digital_OR3 d_or (rise_delay=1e-9 fall_delay=1e-9)
.model Digital_AND2 d_and (rise_delay=1e-9 fall_delay=1e-9)

xbridgeU11 U11_Y 32 AADAC
xbridgeU14 U14_Y 33 AADAC
xbridgeU16 U16_Y 36 AADAC
xbridgeU25 U25_Y 35 AADAC
xbridgeU34 U34_Y 37 AADAC
xbridgeU39 U39_Y 21 AADAC
xbridgeU6 U6_Y 31 AADAC

dd1 8 0vNode1 ledDiodeModel
Vsense1 0vNode1 31 DC 0
* Interactive sense node
b1 lit1 0 v = { if (i(Vsense1) < 0, 0, if( i(Vsense1) > 0.02, 1, { i(Vsense1) / 0.02 })) }

dd2 8 0vNode2 ledDiodeModel
Vsense2 0vNode2 32 DC 0
* Interactive sense node
b2 lit2 0 v = { if (i(Vsense2) < 0, 0, if( i(Vsense2) > 0.02, 1, { i(Vsense2) / 0.02 })) }

dd3 8 0vNode3 ledDiodeModel
Vsense3 0vNode3 21 DC 0
* Interactive sense node
b3 lit3 0 v = { if (i(Vsense3) < 0, 0, if( i(Vsense3) > 0.02, 1, { i(Vsense3) / 0.02 })) }

dd4 8 0vNode4 ledDiodeModel
Vsense4 0vNode4 36 DC 0
* Interactive sense node
b4 lit4 0 v = { if (i(Vsense4) < 0, 0, if( i(Vsense4) > 0.02, 1, { i(Vsense4) / 0.02 })) }

dd5 8 0vNode5 ledDiodeModel
Vsense5 0vNode5 35 DC 0
* Interactive sense node
b5 lit5 0 v = { if (i(Vsense5) < 0, 0, if( i(Vsense5) > 0.02, 1, { i(Vsense5) / 0.02 })) }

dd6 8 0vNode6 ledDiodeModel
Vsense6 0vNode6 33 DC 0
* Interactive sense node
b6 lit6 0 v = { if (i(Vsense6) < 0, 0, if( i(Vsense6) > 0.02, 1, { i(Vsense6) / 0.02 })) }

dd7 8 0vNode7 ledDiodeModel
Vsense7 0vNode7 37 DC 0
* Interactive sense node
b7 lit7 0 v = { if (i(Vsense7) < 0, 0, if( i(Vsense7) > 0.02, 1, { i(Vsense7) / 0.02 })) }

.model ledDiodeModel D( IS=1e-14 N=1 RS=0 IBV=1e-10 BV=1e+30 CJO=0 M=0.5 VJ=1 )

* --- Pin bridge models
.SUBCKT AADAC 1 2
* TIL Driver Model 1 = D/A input, 2 = out
aDACin1 [1] [2] aDAC
.MODEL aDAC dac_bridge (out_low = {lowV} out_high = {highV} out_undef = {unknownV} t_rise = {max(riseT,1e-9)} t_fall = {max(fallT,1e-9)})
.ENDS
.ENDS

* JK0 subcircuit
.subckt Digital_JKFlipFlop_JK0 1 2 3 4 5 6 7 PARAMS: Negative_Edge_Clock=0 Negative_SET_RESET=0 Clk_delay=1n Set_delay=1n Reset_delay=1n Ic=0 Rise_delay=1n Fall_delay=1n

aDG1 neg_SR initSR
aDG2 neg_clk initCLK
A1 [4 neg_SR] set xorset
A2 [3 neg_clk] clk xorclk
A3 [5 neg_SR] reset xorreset
A4 1 2 clk set reset 6 7 JK_FF
**MODELS USED*
.model initCLK d_constsource(State={Negative_Edge_Clock})
.model initSR d_constsource(State={Negative_SET_RESET})
.model xorset d_xor(rise_delay=1e-9 fall_delay=1e-9)
.model xorclk d_xor(rise_delay=1e-9 fall_delay=1e-9)
.model xorreset d_xor(rise_delay=1e-9 fall_delay=1e-9)
.MODEL JK_FF d_jkff (clk_delay={Clk_delay} set_delay={Set_delay} reset_delay={Reset_delay} ic={Ic} rise_delay={Rise_delay} fall_delay={Fall_delay})
.ENDS

* JK1 subcircuit
.subckt Digital_JKFlipFlop_JK1 1 2 3 4 5 6 7 PARAMS: Negative_Edge_Clock=0 Negative_SET_RESET=0 Clk_delay=1n Set_delay=1n Reset_delay=1n Ic=0 Rise_delay=1n Fall_delay=1n

aDG1 neg_SR initSR
aDG2 neg_clk initCLK
A1 [4 neg_SR] set xorset
A2 [3 neg_clk] clk xorclk
A3 [5 neg_SR] reset xorreset
A4 1 2 clk set reset 6 7 JK_FF
**MODELS USED*
.model initCLK d_constsource(State={Negative_Edge_Clock})
.model initSR d_constsource(State={Negative_SET_RESET})
.model xorset d_xor(rise_delay=1e-9 fall_delay=1e-9)
.model xorclk d_xor(rise_delay=1e-9 fall_delay=1e-9)
.model xorreset d_xor(rise_delay=1e-9 fall_delay=1e-9)
.MODEL JK_FF d_jkff (clk_delay={Clk_delay} set_delay={Set_delay} reset_delay={Reset_delay} ic={Ic} rise_delay={Rise_delay} fall_delay={Fall_delay})
.ENDS

* JK2 subcircuit
.subckt Digital_JKFlipFlop_JK2 1 2 3 4 5 6 7 PARAMS: Negative_Edge_Clock=0 Negative_SET_RESET=0 Clk_delay=1n Set_delay=1n Reset_delay=1n Ic=0 Rise_delay=1n Fall_delay=1n

aDG1 neg_SR initSR
aDG2 neg_clk initCLK
A1 [4 neg_SR] set xorset
A2 [3 neg_clk] clk xorclk
A3 [5 neg_SR] reset xorreset
A4 1 2 clk set reset 6 7 JK_FF
**MODELS USED*
.model initCLK d_constsource(State={Negative_Edge_Clock})
.model initSR d_constsource(State={Negative_SET_RESET})
.model xorset d_xor(rise_delay=1e-9 fall_delay=1e-9)
.model xorclk d_xor(rise_delay=1e-9 fall_delay=1e-9)
.model xorreset d_xor(rise_delay=1e-9 fall_delay=1e-9)
.MODEL JK_FF d_jkff (clk_delay={Clk_delay} set_delay={Set_delay} reset_delay={Reset_delay} ic={Ic} rise_delay={Rise_delay} fall_delay={Fall_delay})
.ENDS

* --- Pin bridge models

.SUBCKT REAL_CUSTOM_DAC 1 2 PARAMS: lowV=0 maxLowV=0.8 unknownV=1.0 minHighV=2.0 highV=5.0 riseT=0 fallT=0
* Ideal Driver Model 1 = A/D out, 2 = input
aDACin1 [1] [2] aDAC
.MODEL aDAC dac_bridge (out_low = {lowV} out_high = {highV} out_undef = {unknownV} t_rise = {max(riseT,1e-9)} t_fall = {max(fallT,1e-9)})
.ENDS

.SUBCKT REAL_CUSTOM_ADC 1 2 PARAMS: lowV=0 maxLowV=0.8 unknownV=1.0 minHighV=2.0 highV=5.0 riseT=0 fallT=0
* Ideal Receiver Model 1 = input, 2 = A/D out
aADCin1 [2] [1] ADC
.MODEL ADC adc_bridge (in_low = {maxLowV} in_high = {minHighV})
.ENDS

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Item

Document

Section

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Type

Rise time

Time it takes for signal to transition from low to high.

With non-zero rise time, the signal converts to an analog signal from a digital signal.

Fall time

Time it takes for signal to transition from high to low.

With non-zero fall time, the signal converts to an analog signal from a digital signal.

Use document settings

Use logic levels settings from Document tab.

Threshold voltage levels.

Threshold voltage values used in the logic evaluation. See Digital Simulation for more information.

Output low

Output low voltage.

Maximum output voltage level to produce a low signal.

Input low threshold

Input low threshold voltage.

Maximum input voltage level for the signal to be considered low.

Input high threshold

Input high threshold voltage.

Minimum input voltage level for the signal to be considered high.

Output high

Output high voltage.

Minimum output voltage level to produce a high signal.

Type Probe

Select desired function.

Function

Use document settings

Use logic levels settings from Document tab.

Threshold voltage levels.

Threshold voltage values used in the logic evaluation. See Digital Simulation for more information.

Output low

Output low voltage.

Maximum output voltage level to produce a low signal.

Input low threshold

Input low threshold voltage.

Maximum input voltage level for the signal to be considered low.

Input high threshold

Input high threshold voltage.

Minimum input voltage level for the signal to be considered high.

Output high

Output high voltage.

Minimum output voltage level to produce a high signal.

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Source

Data origin.

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Switch on to stream data from Source when simulation runs.

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Source type

Application used to generate the Source data.

Data type

Type of simulation data in Source.

File size

Size of the referenced file. Total file size for all data plotters cannot exceed 100 MB.

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Data streaming is only available in interactive simulation

Instantaneous

Displays instantaneous measurements on probe during interactive simulation.

Periodic

Displays periodic measurements on probe during Interactive simulation.

Bias point(s)

Displays bias points on probe for DC Op simulation.

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Name Omi Nikolai 4 bit Binary Up Counter

Type Schematic

The simulation to run. See Simulation types for more information.

Name

Title of graph. Edit as desired.

End time

Time at which the simulation stops. Does not include pauses. Simulation does not occur in real time.

Start simulation

RELTOL

Relative error tolerance. A simulation wide accuracy control used to establish convergence.

VNTOL

Absolute voltage error tolerance. Defines the minimum value for voltage where it may still be considered accurate.

ABSTOL

Absolute current error tolerance. Defines the minimum value for current where it may still be considered accurate.

ITL1

DC iteration limit. Number of iterative passes done on DC circuit equations in attempt to reach convergence in simulation.

ITL4

Upper iteration limit. Number of iterative passes done per time point, on Transient circuit equations in attempt to reach convergence in simulation.

Integration method. The numerical integration method used in transient analysis.

Temp

℃

Operating temperature. The temperature at which the entire circuit will be simulated.

Insert shunt resistance

Inserts a resistance of RSHUNT from every analog node to ground. Will aid in convergence, but alter the behavior of the circuit.

RSHUNT

Shunt resistance. This eliminates singular matrix errors that result from a lack of a DC path to ground.

Reset to default

Threshold voltage levels.

Threshold voltage values used in the logic evaluation. See Digital Simulation for more information.

Output low

Output low voltage.

Maximum output voltage level to produce a low signal.

Input low threshold

Input low threshold voltage.

Maximum input voltage level for the signal to be considered low.

Input high threshold

Input high threshold voltage.

Minimum input voltage level for the signal to be considered high.

Output high

Output high voltage.

Minimum output voltage level to produce a high signal.

Width

Sheet width in grid squares.

Height

Sheet height in grid squares.

Grid

Toggles grid display.

Net Labels

Toggles all net labels.

Component Labels

Toggles all component labels.

Omi Nikolai 4 bit Binary Up Counter