*Contador de 4 bits del 0 al 9

Waiting for data

Signal	Value
Signal	Value

Cursor 1	Cursor 2	∆X	1/∆X	∆Y	∆Y (Phase)

Out of date
V	—
V	—
V_PP	—
V_RMS	—
V_AV	—
f_V	—
I	—
I	—
I_PP	—
I_RMS	—
I_AV	—
f_I	—
D	—

Out of date
V	—
V	—
V_PP	—
V_RMS	—
V_AV	—
f_V	—
I	—
I	—
I_PP	—
I_RMS	—
I_AV	—
f_I	—
D	—

Out of date
V	—
V	—
V_PP	—
V_RMS	—
V_AV	—
f_V	—
I	—
I	—
I_PP	—
I_RMS	—
I_AV	—
f_I	—
D	—

Out of date
V	—
V	—
V_PP	—
V_RMS	—
V_AV	—
f_V	—
I	—
I	—
I_PP	—
I_RMS	—
I_AV	—
f_I	—
D	—

Out of date
V	—
V	—
V_PP	—
V_RMS	—
V_AV	—
f_V	—
I	—
I	—
I_PP	—
I_RMS	—
I_AV	—
f_I	—
D	—

ID:

x10

x0.1

Sheet:1

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SPICE

SPICE Netlist

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** Contador de 4 bits del 0 al 9 **
*
* Multisim Live SPICE netlist
*
*

* --- Circuit Topology ---

* Component: DG1
aDG1 2 Digital_Source_DG1

* Component: DG2
aDG2 4 Digital_Source_DG2

* Component: DG3
aDG3 10 Digital_Source_DG3

* Component: DG4
aDG4 6 Digital_Source_DG4

* Component: FFC
xFFC 2 2 1 FFC_NC_SET 8 bridgeFFC!Q 18 Digital_JKFlipFlop_FFC PARAMS: Negative_Edge_Clock=0 Negative_SET_RESET=0 Rise_delay=1e-9 Fall_delay=1e-9 Clk_delay=1e-9 Set_delay=1e-9 Reset_delay=1e-9 Ic=0

xbridgeFFC!Q bridgeFFC!Q 3 REAL_CUSTOM_DAC PARAMS: lowV=0 maxLowV=0.8 unknownV=1 minHighV=2 highV=3.3 riseT=0 fallT=0

* Component: FFC1
xFFC1 4 4 18 FFC1_NC_SET 8 bridgeFFC1!Q 17 Digital_JKFlipFlop_FFC1 PARAMS: Negative_Edge_Clock=0 Negative_SET_RESET=0 Rise_delay=1e-9 Fall_delay=1e-9 Clk_delay=1e-9 Set_delay=1e-9 Reset_delay=1e-9 Ic=0

xbridgeFFC1!Q bridgeFFC1!Q 5 REAL_CUSTOM_DAC PARAMS: lowV=0 maxLowV=0.8 unknownV=1 minHighV=2 highV=3.3 riseT=0 fallT=0

* Component: FFC2
xFFC2 10 10 17 FFC2_NC_SET 8 bridgeFFC2!Q 19 Digital_JKFlipFlop_FFC2 PARAMS: Negative_Edge_Clock=0 Negative_SET_RESET=0 Rise_delay=1e-9 Fall_delay=1e-9 Clk_delay=1e-9 Set_delay=1e-9 Reset_delay=1e-9 Ic=0

xbridgeFFC2!Q bridgeFFC2!Q 11 REAL_CUSTOM_DAC PARAMS: lowV=0 maxLowV=0.8 unknownV=1 minHighV=2 highV=3.3 riseT=0 fallT=0

* Component: FFC3
xFFC3 6 6 19 FFC3_NC_SET 8 bridgeFFC3!Q FFC3_NC_~Q Digital_JKFlipFlop_FFC3 PARAMS: Negative_Edge_Clock=0 Negative_SET_RESET=0 Rise_delay=1e-9 Fall_delay=1e-9 Clk_delay=1e-9 Set_delay=1e-9 Reset_delay=1e-9 Ic=0

xbridgeFFC3!Q bridgeFFC3!Q 7 REAL_CUSTOM_DAC PARAMS: lowV=0 maxLowV=0.8 unknownV=1 minHighV=2 highV=3.3 riseT=0 fallT=0

* Component: LED1
xLED1 3 12 LED_VIRTUAL_LED1

* Component: LED2
xLED2 5 13 LED_VIRTUAL_LED2

* Component: LED3
xLED3 11 14 LED_VIRTUAL_LED3

* Component: LED4
xLED4 7 16 LED_VIRTUAL_LED4

* Component: R1
rR1 12 0 330 VIRTUAL_RESISTANCE_R1

* Component: R2
rR2 13 0 330 VIRTUAL_RESISTANCE_R2

* Component: R3
rR3 14 0 330 VIRTUAL_RESISTANCE_R3

* Component: R4
rR4 16 0 330 VIRTUAL_RESISTANCE_R4

* Component: U1
aU1 [15 bridgeU1!B 9 bridgeU1!D] 8 Digital_AND4_U1

xbridgeU1!B bridgeU1!B 5 REAL_CUSTOM_ADC PARAMS: lowV=0 maxLowV=0.8 unknownV=1 minHighV=2 highV=3.3 riseT=0 fallT=0

xbridgeU1!D bridgeU1!D 7 REAL_CUSTOM_ADC PARAMS: lowV=0 maxLowV=0.8 unknownV=1 minHighV=2 highV=3.3 riseT=0 fallT=0

* Component: U2
aU2 bridgeU2!A 9 Digital_Inverter_U2

xbridgeU2!A bridgeU2!A 11 REAL_CUSTOM_ADC PARAMS: lowV=0 maxLowV=0.8 unknownV=1 minHighV=2 highV=3.3 riseT=0 fallT=0

* Component: U3
aU3 bridgeU3!A 15 Digital_Inverter_U3

xbridgeU3!A bridgeU3!A 3 REAL_CUSTOM_ADC PARAMS: lowV=0 maxLowV=0.8 unknownV=1 minHighV=2 highV=3.3 riseT=0 fallT=0

* Component: clock
xclock 1 Digital_Clock_clock PARAMS: Frequency=10000 Duty=50 Delay=0

* --- Circuit Models ---

* DG1 model
.model Digital_Source_DG1 d_constsource(State=1)

* DG2 model
.model Digital_Source_DG2 d_constsource(State=1)

* DG3 model
.model Digital_Source_DG3 d_constsource(State=1)

* DG4 model
.model Digital_Source_DG4 d_constsource(State=1)

* R1 model
.model VIRTUAL_RESISTANCE_R1 r( )

* R2 model
.model VIRTUAL_RESISTANCE_R2 r( )

* R3 model
.model VIRTUAL_RESISTANCE_R3 r( )

* R4 model
.model VIRTUAL_RESISTANCE_R4 r( )

* U1 model
.model Digital_AND4_U1 d_and (rise_delay=1e-9 fall_delay=1e-9)

* U2 model
.model Digital_Inverter_U2 d_inverter (rise_delay=1e-9 fall_delay=1e-9)

* U3 model
.model Digital_Inverter_U3 d_inverter (rise_delay=1e-9 fall_delay=1e-9)

* --- Subcircuits ---

* FFC subcircuit
.subckt Digital_JKFlipFlop_FFC 1 2 3 4 5 6 7 PARAMS: Negative_Edge_Clock=0 Negative_SET_RESET=0 Clk_delay=1n Set_delay=1n Reset_delay=1n Ic=0 Rise_delay=1n Fall_delay=1n

aDG1 neg_SR initSR
aDG2 neg_clk initCLK
A1 [4 neg_SR] set xorset
A2 [3 neg_clk] clk xorclk
A3 [5 neg_SR] reset xorreset
A4 1 2 clk set reset 6 7 JK_FF
**MODELS USED*
.model initCLK d_constsource(State={Negative_Edge_Clock})
.model initSR d_constsource(State={Negative_SET_RESET})
.model xorset d_xor(rise_delay=1e-9 fall_delay=1e-9)
.model xorclk d_xor(rise_delay=1e-9 fall_delay=1e-9)
.model xorreset d_xor(rise_delay=1e-9 fall_delay=1e-9)
.MODEL JK_FF d_jkff (clk_delay={Clk_delay} set_delay={Set_delay} reset_delay={Reset_delay} ic={Ic} rise_delay={Rise_delay} fall_delay={Fall_delay})
.ENDS

* FFC1 subcircuit
.subckt Digital_JKFlipFlop_FFC1 1 2 3 4 5 6 7 PARAMS: Negative_Edge_Clock=0 Negative_SET_RESET=0 Clk_delay=1n Set_delay=1n Reset_delay=1n Ic=0 Rise_delay=1n Fall_delay=1n

aDG1 neg_SR initSR
aDG2 neg_clk initCLK
A1 [4 neg_SR] set xorset
A2 [3 neg_clk] clk xorclk
A3 [5 neg_SR] reset xorreset
A4 1 2 clk set reset 6 7 JK_FF
**MODELS USED*
.model initCLK d_constsource(State={Negative_Edge_Clock})
.model initSR d_constsource(State={Negative_SET_RESET})
.model xorset d_xor(rise_delay=1e-9 fall_delay=1e-9)
.model xorclk d_xor(rise_delay=1e-9 fall_delay=1e-9)
.model xorreset d_xor(rise_delay=1e-9 fall_delay=1e-9)
.MODEL JK_FF d_jkff (clk_delay={Clk_delay} set_delay={Set_delay} reset_delay={Reset_delay} ic={Ic} rise_delay={Rise_delay} fall_delay={Fall_delay})
.ENDS

* FFC2 subcircuit
.subckt Digital_JKFlipFlop_FFC2 1 2 3 4 5 6 7 PARAMS: Negative_Edge_Clock=0 Negative_SET_RESET=0 Clk_delay=1n Set_delay=1n Reset_delay=1n Ic=0 Rise_delay=1n Fall_delay=1n

aDG1 neg_SR initSR
aDG2 neg_clk initCLK
A1 [4 neg_SR] set xorset
A2 [3 neg_clk] clk xorclk
A3 [5 neg_SR] reset xorreset
A4 1 2 clk set reset 6 7 JK_FF
**MODELS USED*
.model initCLK d_constsource(State={Negative_Edge_Clock})
.model initSR d_constsource(State={Negative_SET_RESET})
.model xorset d_xor(rise_delay=1e-9 fall_delay=1e-9)
.model xorclk d_xor(rise_delay=1e-9 fall_delay=1e-9)
.model xorreset d_xor(rise_delay=1e-9 fall_delay=1e-9)
.MODEL JK_FF d_jkff (clk_delay={Clk_delay} set_delay={Set_delay} reset_delay={Reset_delay} ic={Ic} rise_delay={Rise_delay} fall_delay={Fall_delay})
.ENDS

* FFC3 subcircuit
.subckt Digital_JKFlipFlop_FFC3 1 2 3 4 5 6 7 PARAMS: Negative_Edge_Clock=0 Negative_SET_RESET=0 Clk_delay=1n Set_delay=1n Reset_delay=1n Ic=0 Rise_delay=1n Fall_delay=1n

aDG1 neg_SR initSR
aDG2 neg_clk initCLK
A1 [4 neg_SR] set xorset
A2 [3 neg_clk] clk xorclk
A3 [5 neg_SR] reset xorreset
A4 1 2 clk set reset 6 7 JK_FF
**MODELS USED*
.model initCLK d_constsource(State={Negative_Edge_Clock})
.model initSR d_constsource(State={Negative_SET_RESET})
.model xorset d_xor(rise_delay=1e-9 fall_delay=1e-9)
.model xorclk d_xor(rise_delay=1e-9 fall_delay=1e-9)
.model xorreset d_xor(rise_delay=1e-9 fall_delay=1e-9)
.MODEL JK_FF d_jkff (clk_delay={Clk_delay} set_delay={Set_delay} reset_delay={Reset_delay} ic={Ic} rise_delay={Rise_delay} fall_delay={Fall_delay})
.ENDS

* LED1 subcircuit
.subckt LED_VIRTUAL_LED1 A K

dd1 A 0vNode ledDiodeModel
.model ledDiodeModel D( IS=1e-14 N=1 RS=0 IBV=1e-10 BV=1e+30 CJO=0 M=0.5 VJ=1 )

V_Isense 0vNode K DC 0

* Interactive sense node
b1 lit 0 v = { if (i(V_Isense) < 0, 0, if( i(V_Isense) > 0.005, 1, { i(V_Isense) / 0.005 })) }

.ends

* LED2 subcircuit
.subckt LED_VIRTUAL_LED2 A K

dd1 A 0vNode ledDiodeModel
.model ledDiodeModel D( IS=1e-14 N=1 RS=0 IBV=1e-10 BV=1e+30 CJO=0 M=0.5 VJ=1 )

V_Isense 0vNode K DC 0

* Interactive sense node
b1 lit 0 v = { if (i(V_Isense) < 0, 0, if( i(V_Isense) > 0.005, 1, { i(V_Isense) / 0.005 })) }

.ends

* LED3 subcircuit
.subckt LED_VIRTUAL_LED3 A K

dd1 A 0vNode ledDiodeModel
.model ledDiodeModel D( IS=1e-14 N=1 RS=0 IBV=1e-10 BV=1e+30 CJO=0 M=0.5 VJ=1 )

V_Isense 0vNode K DC 0

* Interactive sense node
b1 lit 0 v = { if (i(V_Isense) < 0, 0, if( i(V_Isense) > 0.005, 1, { i(V_Isense) / 0.005 })) }

.ends

* LED4 subcircuit
.subckt LED_VIRTUAL_LED4 A K

dd1 A 0vNode ledDiodeModel
.model ledDiodeModel D( IS=1e-14 N=1 RS=0 IBV=1e-10 BV=1e+30 CJO=0 M=0.5 VJ=1 )

V_Isense 0vNode K DC 0

* Interactive sense node
b1 lit 0 v = { if (i(V_Isense) < 0, 0, if( i(V_Isense) > 0.005, 1, { i(V_Isense) / 0.005 })) }

.ends

* clock subcircuit
.subckt Digital_Clock_clock out PARAMS: frequency=1000 duty=50 delay=0
a1 clk out
.model clk d_clock(frequency={frequency} duty={duty/100} delay={delay})
.ENDS

* --- Pin bridge models

.SUBCKT REAL_CUSTOM_DAC 1 2 PARAMS: lowV=0 maxLowV=0.8 unknownV=1.0 minHighV=2.0 highV=5.0 riseT=0 fallT=0
* Ideal Driver Model 1 = A/D out, 2 = input
aDACin1 [1] [2] aDAC
.MODEL aDAC dac_bridge (out_low = {lowV} out_high = {highV} out_undef = {unknownV} t_rise = {max(riseT,1e-9)} t_fall = {max(fallT,1e-9)})
.ENDS

.SUBCKT REAL_CUSTOM_ADC 1 2 PARAMS: lowV=0 maxLowV=0.8 unknownV=1.0 minHighV=2.0 highV=5.0 riseT=0 fallT=0
* Ideal Receiver Model 1 = input, 2 = A/D out
aADCin1 [2] [1] ADC
.MODEL ADC adc_bridge (in_low = {maxLowV} in_high = {minHighV})
.ENDS

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Item

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Type

Rise time

Time it takes for signal to transition from low to high.

With non-zero rise time, the signal converts to an analog signal from a digital signal.

Fall time

Time it takes for signal to transition from high to low.

With non-zero fall time, the signal converts to an analog signal from a digital signal.

Use document settings

Use logic levels settings from Document tab.

Threshold voltage levels.

Threshold voltage values used in the logic evaluation. See Digital Simulation for more information.

Output low

Output low voltage.

Maximum output voltage level to produce a low signal.

Input low threshold

Input low threshold voltage.

Maximum input voltage level for the signal to be considered low.

Input high threshold

Input high threshold voltage.

Minimum input voltage level for the signal to be considered high.

Output high

Output high voltage.

Minimum output voltage level to produce a high signal.

Type Probe

Select desired function.

Function

Use document settings

Use logic levels settings from Document tab.

Threshold voltage levels.

Threshold voltage values used in the logic evaluation. See Digital Simulation for more information.

Output low

Output low voltage.

Maximum output voltage level to produce a low signal.

Input low threshold

Input low threshold voltage.

Maximum input voltage level for the signal to be considered low.

Input high threshold

Input high threshold voltage.

Minimum input voltage level for the signal to be considered high.

Output high

Output high voltage.

Minimum output voltage level to produce a high signal.

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RELTOL

Relative error tolerance. A simulation wide accuracy control used to establish convergence.

VNTOL

Absolute voltage error tolerance. Defines the minimum value for voltage where it may still be considered accurate.

ABSTOL

Absolute current error tolerance. Defines the minimum value for current where it may still be considered accurate.

ITL1

DC iteration limit. Number of iterative passes done on DC circuit equations in attempt to reach convergence in simulation.

ITL4

Upper iteration limit. Number of iterative passes done per time point, on Transient circuit equations in attempt to reach convergence in simulation.

Integration method. The numerical integration method used in transient analysis.

Temp

℃

Operating temperature. The temperature at which the entire circuit will be simulated.

Insert shunt resistance

Inserts a resistance of RSHUNT from every analog node to ground. Will aid in convergence, but alter the behavior of the circuit.

RSHUNT

Shunt resistance. This eliminates singular matrix errors that result from a lack of a DC path to ground.

Reset to default

Threshold voltage levels.

Threshold voltage values used in the logic evaluation. See Digital Simulation for more information.

Output low

Output low voltage.

Maximum output voltage level to produce a low signal.

Input low threshold

Input low threshold voltage.

Maximum input voltage level for the signal to be considered low.

Input high threshold

Input high threshold voltage.

Minimum input voltage level for the signal to be considered high.

Output high

Output high voltage.

Minimum output voltage level to produce a high signal.

Width

Sheet width in grid squares.

Height

Sheet height in grid squares.

Grid

Toggles grid display.

Net Labels

Toggles all net labels.

Component Labels

Toggles all component labels.

Contador de 4 bits del 0 al 9