*DC Motor Speed Controller

Waiting for data

Signal	Value
Signal	Value

Cursor 1	Cursor 2	∆X	1/∆X	∆Y	∆Y (Phase)

Out of date
V	—
V	—
V_PP	—
V_RMS	—
V_AV	—
f_V	—
I	—
I	—
I_PP	—
I_RMS	—
I_AV	—
f_I	—
D	—

Out of date
V	—
V	—
V_PP	—
V_RMS	—
V_AV	—
f_V	—
I	—
I	—
I_PP	—
I_RMS	—
I_AV	—
f_I	—
D	—

Out of date
V	—
V	—
V_PP	—
V_RMS	—
V_AV	—
f_V	—
I	—
I	—
I_PP	—
I_RMS	—
I_AV	—
f_I	—
D	—

Out of date
V	—
V	—
V_PP	—
V_RMS	—
V_AV	—
f_V	—
I	—
I	—
I_PP	—
I_RMS	—
I_AV	—
f_I	—
D	—

Out of date
V	—
V	—
V_PP	—
V_RMS	—
V_AV	—
f_V	—
I	—
I	—
I_PP	—
I_RMS	—
I_AV	—
f_I	—
D	—

ID:

x10

x0.1

Sheet:1

Disable streaming

Details

Netlist

Errors

Circuit Details

View and edit circuit details below.

Visibility

Private

Public

Select Public if you want your design to be viewable by all Multisim Live users.

Name

Name of saved file.

Description

Provides context to the design, and an explanation of the circuit operation. This is useful for highlighting theory or critical aspects of the design.

add a tag

Type a string here. Matching tags appear as you type. Tap a matching tag, or enter a new tag.

SPICE

SPICE Netlist

This is a text-based representation of the circuit.
The * symbol indicates a comment.
The + symbol indicates a continuation from the previous line.
Probes do not appear in netlists.

** DC Motor Speed Controller **
*
* Multisim Live SPICE netlist
*
*

* --- Circuit Topology ---

* Component: A1
xA1 0 3 4 5 8 3 6 5 IDEAL_TIMER_A1

* Component: C1
cC1 3 0 1e-8

* Component: C2
cC2 8 0 1e-10

* Component: C3
cC3 7 0 0.00047

* Component: D1
dD1 1 3 DIODE_D1 AREA=1

* Component: D2
dD2 3 2 DIODE_D2 AREA=1

* Component: D3
dD3 7 5 DIODE_D3 AREA=1

* Component: Q1
mQ1 7 6 0 0 PMOS_Q1 L=0.0001 W=0.0001 M=1 AD=0 AS=0 PD=0 PS=0 NRD=1 NRS=1

* Component: R1
rR1 5 6 1000 VIRTUAL_RESISTANCE_R1

* Component: R2
xR2 1 4 2 Potentiometer_R2 PARAMS: res=100000 posPercent=0

* Component: RL
rRL 5 7 600 VIRTUAL_RESISTANCE_RL

* Component: V1
vV1 5 0 dc 9 ac 0 0
+ distof1 0 0
+ distof2 0 0

* --- Circuit Models ---

* D1 model
.model DIODE_D1 D( IS=1e-14 RS=0 N=1 BV=1e+30
+ TT=0 CJO=0 VJ=1 M=0.5 EG=1.11 XTI=3 KF=0 AF=1 FC=0.5 IBV=1e-10
+ IBVL=0 IKF=1e+30 ISR=0 NBV=1 NBVL=1 NR=2 TBV1=0 TBV2=0 TIKF=0
+ TRS1=0 TRS2=0
+ )

* D2 model
.model DIODE_D2 D( IS=1e-14 RS=0 N=1 BV=1e+30
+ TT=0 CJO=0 VJ=1 M=0.5 EG=1.11 XTI=3 KF=0 AF=1 FC=0.5 IBV=1e-10
+ IBVL=0 IKF=1e+30 ISR=0 NBV=1 NBVL=1 NR=2 TBV1=0 TBV2=0 TIKF=0
+ TRS1=0 TRS2=0
+ )

* D3 model
.model DIODE_D3 D( IS=1e-14 RS=0 N=1 BV=1e+30
+ TT=0 CJO=0 VJ=1 M=0.5 EG=1.11 XTI=3 KF=0 AF=1 FC=0.5 IBV=1e-10
+ IBVL=0 IKF=1e+30 ISR=0 NBV=1 NBVL=1 NR=2 TBV1=0 TBV2=0 TIKF=0
+ TRS1=0 TRS2=0
+ )

* Q1 model
.model PMOS_Q1 PMOS( Level=1
+ LAMBDA=0 RD=0 RS=0
+ IS=1e-14 PB=0.8 CGSO=0 CGDO=0 CGBO=0 MJ=0.5
+ MJSW=0.33 JS=0 NSS=0 TPG=1 LD=0 U0=600 KF=0
+AF=1 FC=0.5 RG=0 RB=0 RDS=0 WD=0 N=1 JSSW=0
+TT=0 NLEV=2 GDSNOI=1
+ )

* R1 model
.model VIRTUAL_RESISTANCE_R1 r( )

* RL model
.model VIRTUAL_RESISTANCE_RL r( )

* --- Subcircuits ---

* A1 subcircuit
.subckt IDEAL_TIMER_A1 0 2 3 4 5 6 7 8
rn1 8 5 5k
rn2 5 51 5k
rn3 51 0 5k
Ecomp1 56x 0 value={if(v(5,6)>0,5,0)}
Ecomp2 52x 0 value={if(v(2,51)>0,5,0)}
**These prevent an unstable condition during DC OP
EskipDC 52 0 value={if(TIME>0, v(52x), 0)}
EskipDC2 56 0 value={if(TIME>0, v(56x), 0)}
.model op limit (gain= 3000,
+ out_upper_limit=5,
+ out_lower_limit=-5,
+ limit_range=1 fraction=true)
aadc1 [56 52] [r s] ADC1
.MODEL ADC1 adc_bridge (in_low= 3.5 in_high = 3.5 rise_delay= 1e-12 fall_delay= 1e-12)
anand1 [r Q2] Q1 nand1
anand2 [s Q1] Q2 nand1
.model nand1 d_nand(rise_delay=1n)
adac1 [q1 q2] [66 62] DAC1
rad3 66 0 1
rad4 62 0 1
aadc4 [4] [40] ADC1
ainv2 40 41 inv1
adlatch q1 2u 41 3d Qb Qc dlt
.model dlt d_dlatch(rise_delay=1e-12)
apu1 2u pullup1
.model pullup1 d_pullup(load=10e-12)
apd1 3d pulldown1
.model pulldown1 d_pulldown(load=10e-12)
ainv1 Qb 31 inv1
.model inv1 d_inverter(rise_delay=1e-12)
adac72 [Qb] [72] DAC1
adac31 [31] [32] DAC1
r30 32 0 1g
b1 3 0 v=(v(32)*v(8)/5)
r3 3 0 1g
.MODEL DAC1 dac_bridge (out_low= 0.0 out_high= 5.0 out_undef=0.5)
rad5 72 0 1meg
mdis 7 72 0 0 mdis
.MODEL mdis nmos (VTO=1.29 PHI=0.4 LAMBDA=5 KP=4.3m LD=12.8u GAMMA =3)
.ends

* R2 subcircuit
.subckt Potentiometer_R2 T1 T2 T3 PARAMS: res=10k posPercent=50
.PARAM relPos = limit(posPercent * 0.01, 0.0000001, 0.9999999)
r1 T1 T2 {{res}*relPos}
r2 T2 T3 {{res} - {res}*relPos}
.ends

Errors and Warnings

Any error, warning or information messages appear below.

Item

Document

Section

Only one section is available for multisection components.

Type

Rise time

Time it takes for signal to transition from low to high.

With non-zero rise time, the signal converts to an analog signal from a digital signal.

Fall time

Time it takes for signal to transition from high to low.

With non-zero fall time, the signal converts to an analog signal from a digital signal.

Use document settings

Use logic levels settings from Document tab.

Threshold voltage levels.

Threshold voltage values used in the logic evaluation. See Digital Simulation for more information.

Output low

Output low voltage.

Maximum output voltage level to produce a low signal.

Input low threshold

Input low threshold voltage.

Maximum input voltage level for the signal to be considered low.

Input high threshold

Input high threshold voltage.

Minimum input voltage level for the signal to be considered high.

Output high

Output high voltage.

Minimum output voltage level to produce a high signal.

Type Probe

Select desired function.

Function

Use document settings

Use logic levels settings from Document tab.

Threshold voltage levels.

Threshold voltage values used in the logic evaluation. See Digital Simulation for more information.

Output low

Output low voltage.

Maximum output voltage level to produce a low signal.

Input low threshold

Input low threshold voltage.

Maximum input voltage level for the signal to be considered low.

Input high threshold

Input high threshold voltage.

Minimum input voltage level for the signal to be considered high.

Output high

Output high voltage.

Minimum output voltage level to produce a high signal.

Enter an expression here. You can combine circuit variables with functions and operators to plot an expression in the Grapher.

Activate premium account to edit expression plotters.

Available functions, constants and operators for the expression.

Source

Data origin.

…

Upload a data file here. You can view data from this file in the grapher.

Activate premium account to add/change data files.

Web address of the selected Source.

Activate premium account to add/change data files.

Warning: A popup window will appear.

Connect

Cancel

Connecting

Disconnect

Switch on to stream data from Source when simulation runs.

For data files with more than one plot, select the plot to view.

Source type

Application used to generate the Source data.

Data type

Type of simulation data in Source.

File size

Size of the referenced file. Total file size for all data plotters cannot exceed 100 MB.

Selected simulation type does not match uploaded simulation data

Data streaming is only available in interactive simulation

Instantaneous

Displays instantaneous measurements on probe during interactive simulation.

Periodic

Displays periodic measurements on probe during Interactive simulation.

Bias point(s)

Displays bias points on probe for DC Op simulation.

No items selected.

Name DC Motor Speed Controller

Type Schematic

The simulation to run. See Simulation types for more information.

Name

Title of graph. Edit as desired.

End time

Time at which the simulation stops. Does not include pauses. Simulation does not occur in real time.

Start simulation

RELTOL

Relative error tolerance. A simulation wide accuracy control used to establish convergence.

VNTOL

Absolute voltage error tolerance. Defines the minimum value for voltage where it may still be considered accurate.

ABSTOL

Absolute current error tolerance. Defines the minimum value for current where it may still be considered accurate.

ITL1

DC iteration limit. Number of iterative passes done on DC circuit equations in attempt to reach convergence in simulation.

ITL4

Upper iteration limit. Number of iterative passes done per time point, on Transient circuit equations in attempt to reach convergence in simulation.

Integration method. The numerical integration method used in transient analysis.

Temp

℃

Operating temperature. The temperature at which the entire circuit will be simulated.

Insert shunt resistance

Inserts a resistance of RSHUNT from every analog node to ground. Will aid in convergence, but alter the behavior of the circuit.

RSHUNT

Shunt resistance. This eliminates singular matrix errors that result from a lack of a DC path to ground.

Reset to default

Threshold voltage levels.

Threshold voltage values used in the logic evaluation. See Digital Simulation for more information.

Output low

Output low voltage.

Maximum output voltage level to produce a low signal.

Input low threshold

Input low threshold voltage.

Maximum input voltage level for the signal to be considered low.

Input high threshold

Input high threshold voltage.

Minimum input voltage level for the signal to be considered high.

Output high

Output high voltage.

Minimum output voltage level to produce a high signal.

Width

Sheet width in grid squares.

Height

Sheet height in grid squares.

Grid

Toggles grid display.

Net Labels

Toggles all net labels.

Component Labels

Toggles all component labels.

DC Motor Speed Controller