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GNDDISOUTRSTVCCTHRCONTRI U1100A/AQchg2.2kΩRdpuDdchg100ΩRtf0.1μFCt0.01μFCtl5VVcc0003456PR1PR2PR3100kΩ95%Rtv12VoutVoutPR410kΩR1100A/AQ1VpamVpamPR51kΩR32.8V100Hz0°V1790D10R210kΩ8PR6 V V V V V V
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ID:

ID:
x10
x0.1
Sheet:1
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circuit fundamentals
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555 timer circuits
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555 oscillator
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555 astable multivibrator
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50% duty cycle
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555 square wave generator
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555 timer applications
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555 adjustable frequency
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555 variable frequency
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SPICE
SPICE Netlist

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** PAM con 555 Timer -2 (1) **
*
* Multisim Live SPICE netlist
*
*

* --- Circuit Topology ---

* Component: Ct
cCt 1 0 1e-7

* Component: Ctl
cCtl 5 0 1e-8

* Component: D1
dD1 8 0 DIODE_D1 AREA=1

* Component: Ddchg
dDdchg 4 3 DIODE_Ddchg AREA=1

* Component: Q1
qQ1 8 7 Vpam NPN_Q1 AREA=1

* Component: Qchg
qQchg 6 3 4 NPN_Qchg AREA=1

* Component: R1
rR1 Vout 7 10000 VIRTUAL_RESISTANCE_R1

* Component: R2
rR2 9 Vpam 10000 VIRTUAL_RESISTANCE_R2

* Component: R3
rR3 6 R3_NC_2 1000 VIRTUAL_RESISTANCE_R3

* Component: Rdpu
rRdpu 6 3 2200 VIRTUAL_RESISTANCE_Rdpu

* Component: Rtf
rRtf 4 2 100 VIRTUAL_RESISTANCE_Rtf

* Component: Rtv
xRtv 1 1 2 Potentiometer_Rtv PARAMS: res=100000 posPercent=95

* Component: U1
xU1 0 1 Vout 6 5 1 3 6 IDEAL_TIMER_U1

* Component: V1
vV1 9 0 dc 0 ac 1 0
+ distof1 0 0
+ distof2 0 0
+ sin ( 0 2.8 100 0 0 0 )

* Component: Vcc
vVcc 6 0 dc 5 ac 0 0
+ distof1 0 0
+ distof2 0 0


* --- Circuit Models ---

* D1 model
.model DIODE_D1 D( IS=1e-14 RS=0 N=1 BV=1e+30
+ TT=0 CJO=0 VJ=1 M=0.5 EG=1.11 XTI=3 KF=0 AF=1 FC=0.5 IBV=1e-10
+ IBVL=0 IKF=1e+30 ISR=0 NBV=1 NBVL=1 NR=2 TBV1=0 TBV2=0 TIKF=0
+ TRS1=0 TRS2=0
+ )

* Ddchg model
.model DIODE_Ddchg D( IS=1e-14 RS=0 N=1 BV=1e+30
+ TT=0 CJO=0 VJ=1 M=0.5 EG=1.11 XTI=3 KF=0 AF=1 FC=0.5 IBV=1e-10
+ IBVL=0 IKF=1e+30 ISR=0 NBV=1 NBVL=1 NR=2 TBV1=0 TBV2=0 TIKF=0
+ TRS1=0 TRS2=0
+ )

* Q1 model
.model NPN_Q1 NPN( Level=1
+ IS=1e-16 BF=100 NF=1 VAF=1e+30
+ IKF=1e+30 ISE=0 NE=1.5 BR=1 NR=1 VAR=1e+30 IKR=1e+30 ISC=0 NC=2 RB=0
+ IRB=1e+30 RE=0 RC=0 CJE=0 VJE=0.75 MJE=0.33 TF=0 XTF=0 VTF=1e+30
+ ITF=0 PTF=0 CJC=0 VJC=0.75 MJC=0.33 XCJC=1 TR=0 CJS=0 VJS=0.75 MJS=0
+ XTB=0 EG=1.11 XTI=3 KF=0 AF=1 FC=0.5 NS=1
+ XCJC2=1 XCJS=1 TRB1=0 TRB2=0 TRC1=0 TRC2=0 TRE1=0 TRE2=0 TRM1=0 TRM2=0
+ CN=2.2 D=0.52 GAMMA=1e-11 QCO=0 QUASIMOD=0 RCO=0 VG=1.206 VO=10
+
+ )

* Qchg model
.model NPN_Qchg NPN( Level=1
+ IS=1e-16 BF=100 NF=1 VAF=1e+30
+ IKF=1e+30 ISE=0 NE=1.5 BR=1 NR=1 VAR=1e+30 IKR=1e+30 ISC=0 NC=2 RB=0
+ IRB=1e+30 RE=0 RC=0 CJE=0 VJE=0.75 MJE=0.33 TF=0 XTF=0 VTF=1e+30
+ ITF=0 PTF=0 CJC=0 VJC=0.75 MJC=0.33 XCJC=1 TR=0 CJS=0 VJS=0.75 MJS=0
+ XTB=0 EG=1.11 XTI=3 KF=0 AF=1 FC=0.5 NS=1
+ XCJC2=1 XCJS=1 TRB1=0 TRB2=0 TRC1=0 TRC2=0 TRE1=0 TRE2=0 TRM1=0 TRM2=0
+ CN=2.2 D=0.52 GAMMA=1e-11 QCO=0 QUASIMOD=0 RCO=0 VG=1.206 VO=10
+
+ )

* R1 model
.model VIRTUAL_RESISTANCE_R1 r( )

* R2 model
.model VIRTUAL_RESISTANCE_R2 r( )

* R3 model
.model VIRTUAL_RESISTANCE_R3 r( )

* Rdpu model
.model VIRTUAL_RESISTANCE_Rdpu r( )

* Rtf model
.model VIRTUAL_RESISTANCE_Rtf r( )


* --- Subcircuits ---

* Rtv subcircuit
.subckt Potentiometer_Rtv T1 T2 T3 PARAMS: res=10k posPercent=50
.PARAM relPos = limit(posPercent * 0.01, 0.0000001, 0.9999999)
r1 T1 T2 {{res}*relPos}
r2 T2 T3 {{res} - {res}*relPos}
.ends

* U1 subcircuit
.subckt IDEAL_TIMER_U1 0 2 3 4 5 6 7 8
rn1 8 5 5k
rn2 5 51 5k
rn3 51 0 5k
Ecomp1 56x 0 value={if(v(5,6)>0,5,0)}
Ecomp2 52x 0 value={if(v(2,51)>0,5,0)}
**These prevent an unstable condition during DC OP
EskipDC 52 0 value={if(TIME>0, v(52x), 0)}
EskipDC2 56 0 value={if(TIME>0, v(56x), 0)}
.model op limit (gain= 3000,
+ out_upper_limit=5,
+ out_lower_limit=-5,
+ limit_range=1 fraction=true)
aadc1 [56 52] [r s] ADC1
.MODEL ADC1 adc_bridge (in_low= 3.5 in_high = 3.5 rise_delay= 1e-12 fall_delay= 1e-12)
anand1 [r Q2] Q1 nand1
anand2 [s Q1] Q2 nand1
.model nand1 d_nand(rise_delay=1n)
adac1 [q1 q2] [66 62] DAC1
rad3 66 0 1
rad4 62 0 1
aadc4 [4] [40] ADC1
ainv2 40 41 inv1
adlatch q1 2u 41 3d Qb Qc dlt
.model dlt d_dlatch(rise_delay=1e-12)
apu1 2u pullup1
.model pullup1 d_pullup(load=10e-12)
apd1 3d pulldown1
.model pulldown1 d_pulldown(load=10e-12)
ainv1 Qb 31 inv1
.model inv1 d_inverter(rise_delay=1e-12)
adac72 [Qb] [72] DAC1
adac31 [31] [32] DAC1
r30 32 0 1g
b1 3 0 v=(v(32)*v(8)/5)
r3 3 0 1g
.MODEL DAC1 dac_bridge (out_low= 0.0 out_high= 5.0 out_undef=0.5)
rad5 72 0 1meg
mdis 7 72 0 0 mdis
.MODEL mdis nmos (VTO=1.29 PHI=0.4 LAMBDA=5 KP=4.3m LD=12.8u GAMMA =3)
.ends
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PAM con 555 Timer -2 (1)
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Mode
Threshold voltage levels.

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Output low

V
Output low voltage.

Maximum output voltage level to produce a low signal.

Input low threshold

V
Input low threshold voltage.

Maximum input voltage level for the signal to be considered low.

Input high threshold

V
Input high threshold voltage.

Minimum input voltage level for the signal to be considered high.

Output high

V
Output high voltage.

Minimum output voltage level to produce a high signal.

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