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24VV1022μHL129.5µFC15.00ΩR_Load10.5mΩR_LESRR_CESR20.0mΩV_out0I_InductorS1D_ideal13I_LoadBasic Buck ConverterRun the simulation. Try the following... 1. Adjust the duty cycle using the voltage source "V_Duty" and observe the impact on the output voltage. Notice how the output voltage is equalto the 24V * duty.2. Adjust the value of the capacitor C1. What is the affect on the output voltage ripple?3. Slowly adjust the R_load resistor to change the load current. Does the output always remain at 5V? Observe the inductor current carefully4. Slowly adjust the value of the inductor. What is the effect?5. How does the capacitors ESR (Equivalent Series Resistors) impact the output? This parasitic resistor can be quite significant in the real world.U1205mVV_Duty70PR18PWM generator. Controls the Duty cycle of the PWM generator. 1V=100%. V A A V
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ID:

ID:

x10
x0.1
Sheet:1
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SPICE Netlist

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** Buck Converter **
*
* Multisim Live SPICE netlist
*
*

* --- Circuit Topology ---

* Component: C1
cC1 6 0 0.0000295

* Component: D_ideal
xD_ideal 0 3 DIODE_IDEAL_D_ideal PARAMS: Vf=0 Rdon=0.001 Rdoff=10000000

* Component: L1
lL1 3 4 0.000022

* Component: R_CESR
rR_CESR 5 6 0.02 VIRTUAL_RESISTANCE_R_CESR

* Component: R_LESR
rR_LESR 4 5 0.0105 VIRTUAL_RESISTANCE_R_LESR

* Component: R_Load
rR_Load 5 0 5 VIRTUAL_RESISTANCE_R_Load

* Component: S1
xS1 1 3 8 TRANSISTOR_DIODE_S1 PARAMS: CtrlOn=5 TranRon=0.001 TranRoff=1000000 TranVon=0 DiodeRon=0.01 DiodeRoff=1000000 DiodeVon=0

* Component: U1
xU1 7 8 PWM_U1 PARAMS: Frequency=100000 TriangleMin=0 TriangleMax=1 OutputVoltage=5 RiseFallTime=1e-9 PwmMode=1

* Component: V1
vV1 1 0 dc 24 ac 0 0
+ distof1 0 0
+ distof2 0 0

* Component: V_Duty
vV_Duty 7 0 dc 0.205 ac 0 0
+ distof1 0 0
+ distof2 0 0


* --- Circuit Models ---

* R_CESR model
.model VIRTUAL_RESISTANCE_R_CESR r( )

* R_LESR model
.model VIRTUAL_RESISTANCE_R_LESR r( )

* R_Load model
.model VIRTUAL_RESISTANCE_R_Load r( )


* --- Subcircuits ---

* D_ideal subcircuit
.subckt DIODE_IDEAL_D_ideal a k params: Vf=0 Rdon=1m Rdoff=10meg
ad1 %vd(a k) %id(a k) diode1
.model diode1 pwl(x_array=[{Vf-1} {Vf} {Vf+1}] y_array=[{-1/Rdoff} 0 {1/Rdon}] fraction=false input_domain=0.0)
.ends

* S1 subcircuit
.subckt TRANSISTOR_DIODE_S1 upper lower ctrlp params: CtrlOn=1 TranRon=1 TranRoff=1 TranVon=1 DiodeRon=1 DiodeRoff=1 DiodeVon=1

s1 upper lower_ ctrlp 0 sw1
.model sw1 vswitch(Ron={TranRon} Roff={TranRoff} Von={CtrlOn} Voff=0)

Von lower_ lower {TranVon}

ad1 %vd(lower upper) %id(lower upper) diode1
.model diode1 pwl(x_array=[{DiodeVon-1} {DiodeVon} {DiodeVon+1}] y_array=[{-1/DiodeRoff} 0 {1/DiodeRon}] fraction=false input_domain=0.0)

.ends

* U1 subcircuit
.subckt PWM_U1 in out Params: Frequency=10k TriangleMin=0 TriangleMax=1 OutputVoltage=5 RiseFallTime=1e-9 PWMMode=1

Vf_switch f_switch 0 pulse({TriangleMin} {TriangleMax} 0 {1/2/Frequency} {1/2/Frequency} 0 {1/Frequency})
Acomp out in f_switch pcomp
.model pcomp precision_comparator(output_level={OutputVoltage} rise_fall_time={RiseFallTime} pwm_mode={PWMMode}
+ sawtooth_period={1/Frequency} sawtooth_minimum={TriangleMin} sawtooth_maximum={TriangleMax} peak_time={1/2/Frequency})

.ends

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Buck Converter
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Input high threshold

V

Input high threshold voltage.

Minimum input voltage level for the signal to be considered high.

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V

Output high voltage.

Minimum output voltage level to produce a high signal.

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