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10.0kΩR1R310.0kΩ2U1U21kΩRP1U3U4U52.00kΩ50%RP2100nFCD200ΩRCRD1.00kΩ50%54715131μFCIRI100MΩ50.0%1014310.0kΩR7PR2121msV11010.0kΩR8PR100000100kΩ50%R10U610.0kΩR990161110.0kΩR210.0kΩR4R510.0kΩR610.0kΩ17 V V
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ID:

ID:

x10
x0.1
Sheet:1
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SPICE
SPICE Netlist

This is a text-based representation of the circuit.
The * symbol indicates a comment.
The + symbol indicates a continuation from the previous line.
Probes do not appear in netlists.

** PID Control with op-amp **
*
* Multisim Live SPICE netlist
*
*

* --- Circuit Topology ---

* Component: CD
cCD 3 5 1e-7

* Component: CI
cCI 10 14 0.000001

* Component: R1
rR1 1 2 10000 VIRTUAL_RESISTANCE_R1

* Component: R10
xR10 11 16 16 Potentiometer_R10 PARAMS: res=100000 posPercent=50

* Component: R2
rR2 2 16 10000 VIRTUAL_RESISTANCE_R2

* Component: R3
rR3 2 3 10000 VIRTUAL_RESISTANCE_R3

* Component: R4
rR4 13 17 10000 VIRTUAL_RESISTANCE_R4

* Component: R5
rR5 15 17 10000 VIRTUAL_RESISTANCE_R5

* Component: R6
rR6 14 17 10000 VIRTUAL_RESISTANCE_R6

* Component: R7
rR7 17 12 10000 VIRTUAL_RESISTANCE_R7

* Component: R8
rR8 12 9 10000 VIRTUAL_RESISTANCE_R8

* Component: R9
rR9 9 11 10000 VIRTUAL_RESISTANCE_R9

* Component: RC
rRC 5 7 200 VIRTUAL_RESISTANCE_RC

* Component: RD
xRD 15 7 7 Potentiometer_RD PARAMS: res=1000 posPercent=50

* Component: RI
xRI 10 3 3 Potentiometer_RI PARAMS: res=100000000 posPercent=50

* Component: RP1
rRP1 3 4 1000 VIRTUAL_RESISTANCE_RP1

* Component: RP2
xRP2 13 4 4 Potentiometer_RP2 PARAMS: res=2000 posPercent=50

* Component: U1
xU1 0 2 3 3T_VIRTUAL_U1 PARAMS: VOS=0 IBS=0 IOS=0 AVOL=200000 BW=100000000 RI=10000000 RO=10 VOMP=12 VOMN=-12

* Component: U2
xU2 0 4 13 3T_VIRTUAL_U2 PARAMS: VOS=0 IBS=0 IOS=0 AVOL=200000 BW=100000000 RI=10000000 RO=10 VOMP=12 VOMN=-12

* Component: U3
xU3 0 7 15 3T_VIRTUAL_U3 PARAMS: VOS=0 IBS=0 IOS=0 AVOL=200000 BW=100000000 RI=10000000 RO=10 VOMP=12 VOMN=-12

* Component: U4
xU4 0 10 14 3T_VIRTUAL_U4 PARAMS: VOS=0 IBS=0 IOS=0 AVOL=200000 BW=100000000 RI=10000000 RO=10 VOMP=12 VOMN=-12

* Component: U5
xU5 0 17 12 3T_VIRTUAL_U5 PARAMS: VOS=0 IBS=0 IOS=0 AVOL=200000 BW=100000000 RI=10000000 RO=10 VOMP=12 VOMN=-12

* Component: U6
xU6 0 9 11 3T_VIRTUAL_U6 PARAMS: VOS=0 IBS=0 IOS=0 AVOL=200000 BW=100000000 RI=10000000 RO=10 VOMP=12 VOMN=-12

* Component: V1
vV1 1 0 pwl(0 0 0.001 0 {0.001+1e-8} 5 {0.001+1e-8+1} 5)


* --- Circuit Models ---

* R1 model
.model VIRTUAL_RESISTANCE_R1 r( )

* R2 model
.model VIRTUAL_RESISTANCE_R2 r( )

* R3 model
.model VIRTUAL_RESISTANCE_R3 r( )

* R4 model
.model VIRTUAL_RESISTANCE_R4 r( )

* R5 model
.model VIRTUAL_RESISTANCE_R5 r( )

* R6 model
.model VIRTUAL_RESISTANCE_R6 r( )

* R7 model
.model VIRTUAL_RESISTANCE_R7 r( )

* R8 model
.model VIRTUAL_RESISTANCE_R8 r( )

* R9 model
.model VIRTUAL_RESISTANCE_R9 r( )

* RC model
.model VIRTUAL_RESISTANCE_RC r( )

* RP1 model
.model VIRTUAL_RESISTANCE_RP1 r( )


* --- Subcircuits ---

* R10 subcircuit
.subckt Potentiometer_R10 T1 T2 T3 PARAMS: res=10k posPercent=50
.PARAM relPos = limit(posPercent * 0.01, 0.0000001, 0.9999999)
r1 T1 T2 {{res}*relPos}
r2 T2 T3 {{res} - {res}*relPos}
.ends

* RD subcircuit
.subckt Potentiometer_RD T1 T2 T3 PARAMS: res=10k posPercent=50
.PARAM relPos = limit(posPercent * 0.01, 0.0000001, 0.9999999)
r1 T1 T2 {{res}*relPos}
r2 T2 T3 {{res} - {res}*relPos}
.ends

* RI subcircuit
.subckt Potentiometer_RI T1 T2 T3 PARAMS: res=10k posPercent=50
.PARAM relPos = limit(posPercent * 0.01, 0.0000001, 0.9999999)
r1 T1 T2 {{res}*relPos}
r2 T2 T3 {{res} - {res}*relPos}
.ends

* RP2 subcircuit
.subckt Potentiometer_RP2 T1 T2 T3 PARAMS: res=10k posPercent=50
.PARAM relPos = limit(posPercent * 0.01, 0.0000001, 0.9999999)
r1 T1 T2 {{res}*relPos}
r2 T2 T3 {{res} - {res}*relPos}
.ends

* U1 subcircuit
.SUBCKT 3T_VIRTUAL_U1 in_pos in_neg out PARAMS: AVOL=500k BW=10Meg RI=10Meg RO=0 VOS=0 IBS=0 IOS=0 VOMP=15 VOMN=-15

* Input Stage: Rin, Ibias, Voffset
VOS in_pos 4 {VOS}
Ibias1 4 0 {IBS}
Ibias2 in_neg 0 {IBS}
Ios 4 in_neg {IOS/2}
Rin 4 in_neg {RI}

*Middle stage: Gain, frequency, voltage limiting
Bgain 0 6 I={v(4,in_neg)*AVOL/1meg }
R1 6 0 1meg
CP1 6 0 {AVOL/(2*pi*1meg*BW)}


Vpos 9 0 {VOMP}
Dlimit_pos 6 9 d1

Vneg 10 0 {VOMN}
Dlimit_neg 10 6 d1

.model d1 d(n=0.1)

*Output stage: Buffer, output resistance
E2 7 0 6 0 1
Rout 7 out {RO}
.ends

* U2 subcircuit
.SUBCKT 3T_VIRTUAL_U2 in_pos in_neg out PARAMS: AVOL=500k BW=10Meg RI=10Meg RO=0 VOS=0 IBS=0 IOS=0 VOMP=15 VOMN=-15

* Input Stage: Rin, Ibias, Voffset
VOS in_pos 4 {VOS}
Ibias1 4 0 {IBS}
Ibias2 in_neg 0 {IBS}
Ios 4 in_neg {IOS/2}
Rin 4 in_neg {RI}

*Middle stage: Gain, frequency, voltage limiting
Bgain 0 6 I={v(4,in_neg)*AVOL/1meg }
R1 6 0 1meg
CP1 6 0 {AVOL/(2*pi*1meg*BW)}


Vpos 9 0 {VOMP}
Dlimit_pos 6 9 d1

Vneg 10 0 {VOMN}
Dlimit_neg 10 6 d1

.model d1 d(n=0.1)

*Output stage: Buffer, output resistance
E2 7 0 6 0 1
Rout 7 out {RO}
.ends

* U3 subcircuit
.SUBCKT 3T_VIRTUAL_U3 in_pos in_neg out PARAMS: AVOL=500k BW=10Meg RI=10Meg RO=0 VOS=0 IBS=0 IOS=0 VOMP=15 VOMN=-15

* Input Stage: Rin, Ibias, Voffset
VOS in_pos 4 {VOS}
Ibias1 4 0 {IBS}
Ibias2 in_neg 0 {IBS}
Ios 4 in_neg {IOS/2}
Rin 4 in_neg {RI}

*Middle stage: Gain, frequency, voltage limiting
Bgain 0 6 I={v(4,in_neg)*AVOL/1meg }
R1 6 0 1meg
CP1 6 0 {AVOL/(2*pi*1meg*BW)}


Vpos 9 0 {VOMP}
Dlimit_pos 6 9 d1

Vneg 10 0 {VOMN}
Dlimit_neg 10 6 d1

.model d1 d(n=0.1)

*Output stage: Buffer, output resistance
E2 7 0 6 0 1
Rout 7 out {RO}
.ends

* U4 subcircuit
.SUBCKT 3T_VIRTUAL_U4 in_pos in_neg out PARAMS: AVOL=500k BW=10Meg RI=10Meg RO=0 VOS=0 IBS=0 IOS=0 VOMP=15 VOMN=-15

* Input Stage: Rin, Ibias, Voffset
VOS in_pos 4 {VOS}
Ibias1 4 0 {IBS}
Ibias2 in_neg 0 {IBS}
Ios 4 in_neg {IOS/2}
Rin 4 in_neg {RI}

*Middle stage: Gain, frequency, voltage limiting
Bgain 0 6 I={v(4,in_neg)*AVOL/1meg }
R1 6 0 1meg
CP1 6 0 {AVOL/(2*pi*1meg*BW)}


Vpos 9 0 {VOMP}
Dlimit_pos 6 9 d1

Vneg 10 0 {VOMN}
Dlimit_neg 10 6 d1

.model d1 d(n=0.1)

*Output stage: Buffer, output resistance
E2 7 0 6 0 1
Rout 7 out {RO}
.ends

* U5 subcircuit
.SUBCKT 3T_VIRTUAL_U5 in_pos in_neg out PARAMS: AVOL=500k BW=10Meg RI=10Meg RO=0 VOS=0 IBS=0 IOS=0 VOMP=15 VOMN=-15

* Input Stage: Rin, Ibias, Voffset
VOS in_pos 4 {VOS}
Ibias1 4 0 {IBS}
Ibias2 in_neg 0 {IBS}
Ios 4 in_neg {IOS/2}
Rin 4 in_neg {RI}

*Middle stage: Gain, frequency, voltage limiting
Bgain 0 6 I={v(4,in_neg)*AVOL/1meg }
R1 6 0 1meg
CP1 6 0 {AVOL/(2*pi*1meg*BW)}


Vpos 9 0 {VOMP}
Dlimit_pos 6 9 d1

Vneg 10 0 {VOMN}
Dlimit_neg 10 6 d1

.model d1 d(n=0.1)

*Output stage: Buffer, output resistance
E2 7 0 6 0 1
Rout 7 out {RO}
.ends

* U6 subcircuit
.SUBCKT 3T_VIRTUAL_U6 in_pos in_neg out PARAMS: AVOL=500k BW=10Meg RI=10Meg RO=0 VOS=0 IBS=0 IOS=0 VOMP=15 VOMN=-15

* Input Stage: Rin, Ibias, Voffset
VOS in_pos 4 {VOS}
Ibias1 4 0 {IBS}
Ibias2 in_neg 0 {IBS}
Ios 4 in_neg {IOS/2}
Rin 4 in_neg {RI}

*Middle stage: Gain, frequency, voltage limiting
Bgain 0 6 I={v(4,in_neg)*AVOL/1meg }
R1 6 0 1meg
CP1 6 0 {AVOL/(2*pi*1meg*BW)}


Vpos 9 0 {VOMP}
Dlimit_pos 6 9 d1

Vneg 10 0 {VOMN}
Dlimit_neg 10 6 d1

.model d1 d(n=0.1)

*Output stage: Buffer, output resistance
E2 7 0 6 0 1
Rout 7 out {RO}
.ends

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PID Control with op-amp
Schematic

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Name

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Start time

s

Time simulation output is first plotted from. Simulation does not occur in real time.

End time

s

Time at which the simulation stops. Does not include pauses. Simulation does not occur in real time.

Start simulation

Mode

Threshold voltage levels.

Threshold voltage values used in the logic evaluation. See Digital Simulation for more information.

Output low

V

Output low voltage.

Maximum output voltage level to produce a low signal.

Input low threshold

V

Input low threshold voltage.

Maximum input voltage level for the signal to be considered low.

Input high threshold

V

Input high threshold voltage.

Minimum input voltage level for the signal to be considered high.

Output high

V

Output high voltage.

Minimum output voltage level to produce a high signal.

Width

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Height

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