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VoutADJVin 24.0VV1LM317HU1270ΩR1R22.25kΩ300A/AQ1301kΩR34LM324ANGU2A50R4100mΩ0RN6.30ΩPR11N4148D110μFC10C21000μF010nFC372910ΩR640A/AQ21R74.30kΩ2.7VD2100R810kΩ043.0kΩR9111μFC400 VA
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ID:

ID:

x10
x0.1
Sheet:1
V
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SPICE
SPICE Netlist

This is a text-based representation of the circuit.
The * symbol indicates a comment.
The + symbol indicates a continuation from the previous line.
Probes do not appear in netlists.

** LM317 5A current limiter (1) **
*
* Multisim Live SPICE netlist
*
*

* --- Circuit Topology ---

* Component: C1
cC1 3 0 0.00001

* Component: C2
cC2 9 0 0.001

* Component: C3
cC3 5 11 1e-8

* Component: C4
cC4 10 0 0.000001

* Component: D1
dD1 3 9 1N4148_2_D1

* Component: D2
aD2 0 10 ZENER_VIRTUAL_D2

* Component: Q1
qQ1 3 4 0 NPN_Q1 AREA=1

* Component: Q2
qQ2 9 2 1 PNP_Q2 AREA=1

* Component: R1
rR1 9 3 270 VIRTUAL_RESISTANCE_R1

* Component: R2
rR2 3 7 2250 VIRTUAL_RESISTANCE_R2

* Component: R3
rR3 4 5 1000 VIRTUAL_RESISTANCE_R3

* Component: R4
rR4 0 7 0.1 VIRTUAL_RESISTANCE_R4

* Component: R6
rR6 1 2 10 VIRTUAL_RESISTANCE_R6

* Component: R7
rR7 1 10 4300 VIRTUAL_RESISTANCE_R7

* Component: R8
rR8 11 0 10000 VIRTUAL_RESISTANCE_R8

* Component: R9
rR9 10 11 43000 VIRTUAL_RESISTANCE_R9

* Component: RN
rRN 9 7 6.3 VIRTUAL_RESISTANCE_RN

* Component: U1
xU1 2 9 3 UPC317H_U1

* Component: U2A
xU2A 7 11 1 0 5 LM224_ON/ON_U2A

* Component: V1
vV1 1 0 dc 24 ac 0 0
+ distof1 0 0
+ distof2 0 0


* --- Circuit Models ---

* D1 model
.model 1N4148_2_D1 d (
+ IS=6.89131e-09 RS=0.636257 N=1.82683 EG=1.15805
+ XTI=0.518861 BV=80 IBV=0.0001 CJO=9.99628e-13
+ VJ=0.942987 M=0.727538 FC=0.5 TT=4.33674e-09
+ KF=0 AF=1 )

* D2 model
.model ZENER_VIRTUAL_D2 ZENER ( v_breakdown=2.7 i_breakdown=0.02 i_sat=1e-12 n_forward=1 )

* Q1 model
.model NPN_Q1 NPN( Level=1
+ IS=1e-16 BF=300 NF=1 VAF=1e+30
+ IKF=1e+30 ISE=0 NE=1.5 BR=1 NR=1 VAR=1e+30 IKR=1e+30 ISC=0 NC=2 RB=0
+ IRB=1e+30 RE=0 RC=0 CJE=0 VJE=0.75 MJE=0.33 TF=0 XTF=0 VTF=1e+30
+ ITF=0 PTF=0 CJC=0 VJC=0.75 MJC=0.33 XCJC=1 TR=0 CJS=0 VJS=0.75 MJS=0
+ XTB=0 EG=1.11 XTI=3 KF=0 AF=1 FC=0.5 NS=1
+ XCJC2=1 XCJS=1 TRB1=0 TRB2=0 TRC1=0 TRC2=0 TRE1=0 TRE2=0 TRM1=0 TRM2=0
+ CN=2.2 D=0.52 GAMMA=1e-11 QCO=0 QUASIMOD=0 RCO=0 VG=1.206 VO=10
+
+ )

* Q2 model
.model PNP_Q2 PNP( Level=1
+ IS=1e-16 BF=40 NF=1 VAF=1e+30
+ IKF=1e+30 ISE=0 NE=1.5 BR=1 NR=1 VAR=1e+30 IKR=1e+30 ISC=0 NC=2 RB=0
+ IRB=1e+30 RE=0 RC=0 CJE=0 VJE=0.75 MJE=0.33 TF=0 XTF=0 VTF=1e+30
+ ITF=0 PTF=0 CJC=0 VJC=0.75 MJC=0.33 XCJC=1 TR=0 CJS=0 VJS=0.75 MJS=0
+ XTB=0 EG=1.11 XTI=3 KF=0 AF=1 FC=0.5 NS=1
+ XCJC2=1 XCJS=1 TRB1=0 TRB2=0 TRC1=0 TRC2=0 TRE1=0 TRE2=0 TRM1=0 TRM2=0
+ CN=2.2 D=0.52 GAMMA=1e-11 QCO=0 QUASIMOD=0 RCO=0 VG=1.206 VO=10
+
+ )

* R1 model
.model VIRTUAL_RESISTANCE_R1 r( )

* R2 model
.model VIRTUAL_RESISTANCE_R2 r( )

* R3 model
.model VIRTUAL_RESISTANCE_R3 r( )

* R4 model
.model VIRTUAL_RESISTANCE_R4 r( )

* R6 model
.model VIRTUAL_RESISTANCE_R6 r( )

* R7 model
.model VIRTUAL_RESISTANCE_R7 r( )

* R8 model
.model VIRTUAL_RESISTANCE_R8 r( )

* R9 model
.model VIRTUAL_RESISTANCE_R9 r( )

* RN model
.model VIRTUAL_RESISTANCE_RN r( )


* --- Subcircuits ---

* U1 subcircuit
.subckt UPC317H_U1 3 1 2
* Model Generated by MODPEX *
*Copyright(c) Symmetry Design Systems*
* All Rights Reserved *
* UNPUBLISHED LICENSED SOFTWARE *
* Contains Proprietary Information *
* Which is The Property of *
* SYMMETRY OR ITS LICENSORS *
*Commercial Use or Resale Restricted *
* by Symmetry License Agreement *
* Model generated on Sep 8, 97
* MODEL FORMAT: SPICE3
*Rev. Date: Dec. 20, 1994
*Positive Adjustable Regulator
*External Node Designations
*node 1: VREF (OUTPUT)
*node 2: Ground (Common)
*node 3: Line Voltage
ECCX 131 2 135 2 1.0
VXX 133 2 DC 0
FSET6 2 135 VSENS2 1
FPP 3 2 VXX 1.0
R_YY 31 2 1e6
R_XX 15 2 1e8
R_ZZ 36 2 1e6
R_QQ 65 2 1e8
RXX 1 2 1e8
VSENS1 10 1 DC 0
ISET 2 15 DC 1e-3
DON1 15 16 DMOD1
VSENS2 16 19 DC 0
DON2 15 17 DMOD1
EON2 18 2 3 2 1
FYY 3 2 VSENS1 1
DON3 15 27 DMOD1
VDROP3 28 27 DC 2
EON3 28 2 3 2 4
ELINE 13 42 66 2 1
FSET2 2 36 VSENS2 1
DSC1 36 35 DMOD1
RCL1 36 37 10
DSC2 37 38 DMOD1
ESCCON 38 39 30 2 1
VSCCON 39 40 DC 0
FSC 19 2 VSCCON 1
FSET3 2 31 VSENS2 1
DOV1 31 32 DMOD1
EOV1 32 2 3 1 1
DOV2 31 33 DMOD1
ISET4 2 30 DC 1e-3
ELOAD 41 2 77 2 -1
ERIPPLE 42 41 72 2 1
EREF 12 13 19 2 1
E3 52 2 3 2 1
CBYPS 54 2 0.001
VORB 54 60 DC 0
RB 60 2 1e3
RBR 72 2 1000
CBS2 52 71 1
RSTEP 77 2 1
FRB 2 65 VORB 1
DRB2 65 67 DMOD1
VXRB 67 68 DC -1
EXRB 68 2 1 2 1
DRB1 65 66 DMOD1
RB1 66 2 1000
.MODEL DMOD1 D
*-- DMOD1 DEFAULT PARAMETERS
*IS=1e-14 RS=0 N=1 TT=0 CJO=0
*VJ=1 M=0.5 EG=1.11 XTI=3 FC=0.5
*KF=0 AF=1 BV=inf IBV=1e-3 TNOM=27
EXX 132 131 3 131 0.006
RST6 135 2 10000
RIQX 133 132 RQIX 200000
.MODEL RQIX R TC1=-0.001
RSET 19 2 RSET 1250
.MODEL RSET R TC1=2e-05 TC2=9.8e-08
RS1 10 12 0.0033
VDROPX 18 17 1.26
HSENSE1 35 2 VSENS1 4.54545
RISC 30 2 RISC 10000
.MODEL RISC R TC1=-0.0006
ROV 34 2 35000
VOV 33 34 15
EOV2 2 40 34 2 0.181818
FIQD 3 2 VSENS1 1e-07
RY 52 54 8e+06
RA 72 73 2177.21
RYR 71 72 315228
CRA 52 73 1.67142e-09
HSTEP 76 2 VSENS1 0.2
CSTEP 76 77 1e-05
.ENDS upc317h

* U2A subcircuit
*****
* (c) ON SEMICONDUCTOR
* Models developed and under copyright by:
* ON SEMICONDUCTOR
* ============================================================
* | Legal Notice: This material is intended for free
* | software support. The file may be copied and distributed.
* | However,reselling the material is illegal.
* ============================================================
* ============================================================
* | LM224, LM324, LM324A, LM2902, LM2902V, NCV2902
* | OP-AMP MACRO-MODEL
* | Designed in pSpice Version 9.2
* |
* | The content of this model is subject to change
* | without notice and may not be modified or altered
* | without permission from ON Semiconductor. This model
* | has been carefully checked and is believed to be
* | accurate, however ON Semiconductor does not assume
* | liability for the use of this model or the results
* | obtained from using it.
* ============================================================
* ============================================================
* Features: - True Differential Input Stage
* - Single Supply Operation: 3.0 V to 32 V
* - Low Input Bias Currents: 100 nA Maximum (LM324A)
* - Internally Compensated
* - Common Mode Range Extends to Negative Supply
* ============================================================
* $Author: Vallabh Chilakapati $
* $Date: 4 Aug 2006 $
* NOTE: - Noise is not modeled.
* - Temperature is not modeled.
* - PSR is not modeled.
* - Model is for single device only. Simulated supply current is 1/2 of
* total package current.
* Connections:
* Non-Inverting Input
* | Inverting Input
* | | +ve Supply Voltage
* | | | -ve Supply Voltage
* | | | | Output
* | | | | |
.subckt LM224_ON/ON_U2A 1 2 11 12 24

***** Input Stage *****
Q_Q1 4 5 6 QPNP1
Q_Q2 7 8 9 QPNP2
I_I1 111 10 DC 1m
R_RC1 4 12 95.49
R_RC2 7 12 95.49
R_RE1 10 6 43.79
R_RE2 10 9 43.79
V_Vio 2 8 0Vdc
E_E4 1 5 16 14 1
E_EVcc 111 0 11 0 1
G_Vcc 0 11 poly(1) 11 0 0.278m 2.4u

***** Gain Stage & Frequency Response Stage *****
R_R3 13 12 1000
R_R4 111 13 100k
E_Eref 14 0 13 0 1
G_G1 14 15 7 4 0.01047
R_Rc 14 15 9.549Meg
C_Cc 14 15 1.667n

***** Output Stage *****
E_E1 22 14 15 14 1
V_F1 23 24 0
F_F1 11 0 V_F1 1
R_Rout 22 23 13

***** Common Mode Rejection *****
R_R1 3 1 1Meg
R_R2 2 3 1Meg
G_G2 14 16 3 14 5.6234n
R_Rcmr 17 16 10k
L_Lcmr 14 17 1.59H

***** Output Voltage Limiting *****
D_D1 15 18 D10D1
D_D2 19 15 D10D1
V_Voh 111 18 2.19
V_Vol 19 12 0.63

***** Output Current Limiting *****
D_D3 15 21 D10D1
D_D4 20 15 D10D1
V_V3 21 23 -0.207
V_V4 23 20 -0.467

***** Models *****
.model QPNP1 PNP(Bf=6041.7)
.model QPNP2 PNP(Bf=5186.8)
.MODEL D10D1 D IS=1E-15 RS=1.000E-3 VJ=.75 BV=100E6
.ENDS

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LM317 5A current limiter (1)
Schematic

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Name

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End time

s

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Mode

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Threshold voltage values used in the logic evaluation. See Digital Simulation for more information.

Output low

V

Output low voltage.

Maximum output voltage level to produce a low signal.

Input low threshold

V

Input low threshold voltage.

Maximum input voltage level for the signal to be considered low.

Input high threshold

V

Input high threshold voltage.

Minimum input voltage level for the signal to be considered high.

Output high

V

Output high voltage.

Minimum output voltage level to produce a high signal.

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