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JK flip-flop

This component is a JK flip-flop with preset, clear and complementary outputs. The J and K inputs must be stable prior to the LOW-to-HIGH clock transition for predictable operation. The preset and clear are asynchronous active low inputs. When low, they override the clock and data inputs forcing the outputs to the steady state levels.

JK flip flop conpane.PNG

Function table

JK Flip-Flop