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D Q ~Q RESET CLK SET D Q ~Q RESET CLK SET D Q ~Q RESET CLK SET D Q ~Q RESET CLK SET U1U2U3U4U5U6U7U8U9U10U11U12U13DG1DG2DG3DG4DG5123456789101112DG61314U1415161718190LED1200PR1PR2PR3PR4PR5PR6 0/1 0/1 0/1 0/1 0/1 0/1
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ID:

ID:
x10
x0.1
Sheet:1
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SPICE
SPICE Netlist

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** RA1911028010003.EXP9(c) **
*
* Multisim Live SPICE netlist
*
*

* --- Circuit Topology ---

* Component: DG1
aDG1 15 Digital_Source_DG1

* Component: DG2
aDG2 14 Digital_Source_DG2

* Component: DG3
aDG3 1 Digital_Source_DG3

* Component: DG4
aDG4 2 Digital_Source_DG4

* Component: DG5
aDG5 3 Digital_Source_DG5

* Component: DG6
aDG6 13 Digital_Source_DG6

* Component: LED1
xLED1 20 0 LED_VIRTUAL_LED1

* Component: U1
aU1 14 13 U1_NC_SET bridgeU1!RESET 17 U1_NC_~Q Digital_DFlipFlopPOSSR_U1

xbridgeU1!RESET bridgeU1!RESET 0 REAL_CUSTOM_ADC PARAMS: lowV=0 maxLowV=0.8 unknownV=1 minHighV=2 highV=5 riseT=0 fallT=0

* Component: U10
aU10 [3 16] 9 Digital_AND2_U10

* Component: U11
aU11 [5 4] 12 Digital_OR2_U11

* Component: U12
aU12 [7 6] 11 Digital_OR2_U12

* Component: U13
aU13 [9 8] 10 Digital_OR2_U13

* Component: U14
aU14 15 16 Digital_Inverter_U14

* Component: U2
aU2 12 13 U2_NC_SET bridgeU2!RESET 18 U2_NC_~Q Digital_DFlipFlopPOSSR_U2

xbridgeU2!RESET bridgeU2!RESET 0 REAL_CUSTOM_ADC PARAMS: lowV=0 maxLowV=0.8 unknownV=1 minHighV=2 highV=5 riseT=0 fallT=0

* Component: U3
aU3 11 13 U3_NC_SET bridgeU3!RESET 19 U3_NC_~Q Digital_DFlipFlopPOSSR_U3

xbridgeU3!RESET bridgeU3!RESET 0 REAL_CUSTOM_ADC PARAMS: lowV=0 maxLowV=0.8 unknownV=1 minHighV=2 highV=5 riseT=0 fallT=0

* Component: U4
aU4 10 13 U4_NC_SET bridgeU4!RESET bridgeU4!Q U4_NC_~Q Digital_DFlipFlopPOSSR_U4

xbridgeU4!RESET bridgeU4!RESET 0 REAL_CUSTOM_ADC PARAMS: lowV=0 maxLowV=0.8 unknownV=1 minHighV=2 highV=5 riseT=0 fallT=0

xbridgeU4!Q bridgeU4!Q 20 REAL_CUSTOM_DAC PARAMS: lowV=0 maxLowV=0.8 unknownV=1 minHighV=2 highV=5 riseT=0 fallT=0

* Component: U5
aU5 [15 17] 4 Digital_AND2_U5

* Component: U6
aU6 [1 16] 5 Digital_AND2_U6

* Component: U7
aU7 [15 18] 6 Digital_AND2_U7

* Component: U8
aU8 [2 16] 7 Digital_AND2_U8

* Component: U9
aU9 [15 19] 8 Digital_AND2_U9


* --- Circuit Models ---

* DG1 model
.model Digital_Source_DG1 d_constsource(State=0)

* DG2 model
.model Digital_Source_DG2 d_constsource(State=1)

* DG3 model
.model Digital_Source_DG3 d_constsource(State=1)

* DG4 model
.model Digital_Source_DG4 d_constsource(State=0)

* DG5 model
.model Digital_Source_DG5 d_constsource(State=1)

* DG6 model
.model Digital_Source_DG6 d_constsource(State=0)

* U1 model
.model Digital_DFlipFlopPOSSR_U1 d_dff (rise_delay=1e-9 fall_delay=1e-9 clk_delay=1e-9 set_delay=1e-9 reset_delay=1e-9 ic=0)

* U10 model
.model Digital_AND2_U10 d_and (rise_delay=1e-9 fall_delay=1e-9)

* U11 model
.model Digital_OR2_U11 d_or (rise_delay=1e-9 fall_delay=1e-9)

* U12 model
.model Digital_OR2_U12 d_or (rise_delay=1e-9 fall_delay=1e-9)

* U13 model
.model Digital_OR2_U13 d_or (rise_delay=1e-9 fall_delay=1e-9)

* U14 model
.model Digital_Inverter_U14 d_inverter (rise_delay=1e-9 fall_delay=1e-9)

* U2 model
.model Digital_DFlipFlopPOSSR_U2 d_dff (rise_delay=1e-9 fall_delay=1e-9 clk_delay=1e-9 set_delay=1e-9 reset_delay=1e-9 ic=0)

* U3 model
.model Digital_DFlipFlopPOSSR_U3 d_dff (rise_delay=1e-9 fall_delay=1e-9 clk_delay=1e-9 set_delay=1e-9 reset_delay=1e-9 ic=0)

* U4 model
.model Digital_DFlipFlopPOSSR_U4 d_dff (rise_delay=1e-9 fall_delay=1e-9 clk_delay=1e-9 set_delay=1e-9 reset_delay=1e-9 ic=0)

* U5 model
.model Digital_AND2_U5 d_and (rise_delay=1e-9 fall_delay=1e-9)

* U6 model
.model Digital_AND2_U6 d_and (rise_delay=1e-9 fall_delay=1e-9)

* U7 model
.model Digital_AND2_U7 d_and (rise_delay=1e-9 fall_delay=1e-9)

* U8 model
.model Digital_AND2_U8 d_and (rise_delay=1e-9 fall_delay=1e-9)

* U9 model
.model Digital_AND2_U9 d_and (rise_delay=1e-9 fall_delay=1e-9)


* --- Subcircuits ---

* LED1 subcircuit
.subckt LED_VIRTUAL_LED1 A K

dd1 A 0vNode ledDiodeModel
.model ledDiodeModel D( IS=1e-14 N=1 RS=0 IBV=1e-10 BV=1e+30 CJO=0 M=0.5 VJ=1 )

V_Isense 0vNode K DC 0

* Interactive sense node
b1 lit 0 v = { if (i(V_Isense) < 0, 0, if( i(V_Isense) > 0.005, 1, { i(V_Isense) / 0.005 })) }

.ends


* --- Pin bridge models

.SUBCKT REAL_CUSTOM_ADC 1 2 PARAMS: lowV=0 maxLowV=0.8 unknownV=1.0 minHighV=2.0 highV=5.0 riseT=0 fallT=0
* Ideal Receiver Model 1 = input, 2 = A/D out
aADCin1 [2] [1] ADC
.MODEL ADC adc_bridge (in_low = {maxLowV} in_high = {minHighV})
.ENDS

.SUBCKT REAL_CUSTOM_DAC 1 2 PARAMS: lowV=0 maxLowV=0.8 unknownV=1.0 minHighV=2.0 highV=5.0 riseT=0 fallT=0
* Ideal Driver Model 1 = A/D out, 2 = input
aDACin1 [1] [2] aDAC
.MODEL aDAC dac_bridge (out_low = {lowV} out_high = {highV} out_undef = {unknownV} t_rise = {max(riseT,1e-9)} t_fall = {max(fallT,1e-9)})
.ENDS
Errors and Warnings

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TypeDescription
A component update replaced the model for component U1 with a newer version. Check your simulation results.
A component update replaced the model for component U2 with a newer version. Check your simulation results.
A component update replaced the model for component U3 with a newer version. Check your simulation results.
A component update replaced the model for component U4 with a newer version. Check your simulation results.
A component update replaced the symbol for component U1 with a newer version. Check your schematic.
A component update replaced the symbol for component U2 with a newer version. Check your schematic.
A component update replaced the symbol for component U3 with a newer version. Check your schematic.
A component update replaced the symbol for component U4 with a newer version. Check your schematic.
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RA1911028010003.EXP9(c)
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s

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Threshold voltage levels.

Threshold voltage values used in the logic evaluation. See Digital Simulation for more information.

Output low

V
Output low voltage.

Maximum output voltage level to produce a low signal.

Input low threshold

V
Input low threshold voltage.

Maximum input voltage level for the signal to be considered low.

Input high threshold

V
Input high threshold voltage.

Minimum input voltage level for the signal to be considered high.

Output high

V
Output high voltage.

Minimum output voltage level to produce a high signal.

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