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MAJ CEAASE

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MAJ CEAASE
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D flip-flop created from NAND gates, using clock voltage as the data source. I recommend setting the Grapher time range from 0-5 seconds after running the simulation.

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Profile image for krishh015

krishh015

5 Circuits

Date Created

1 year, 4 months ago

Last Modified

1 year, 4 months ago

Tags

  • digital
  • nand gate
  • flip-flop

Circuit Copied From

D flip-flop

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