SR Latch

A storage element in a digital circuit can maintain a binary state indefinitely (as long as power is delivered to the circuit), until directed by an input signal to switch states. •The major differences among various types of storage elements are in the number of inputs they possess and in the manner in which the inputs affect the binary state. •Storage elements that operate with signal levels (rather than signal transitions) are referred to as latches ; those controlled by a clock transition are flip-flops. •Latches are said to be level sensitive devices; flip-flops are edge-sensitive devices. •The two types of storage elements are related because latches are the basic circuits from which all flip-flops are constructed. •latches are useful for storing binary information •Basically Latches are the building blocks of flip-flops. •The SR latch is a circuit with two cross-coupled NOR gates or two cross-coupled NAND gates, and two inputs labeled S for set and R for reset. D latch (transparent):- One way to eliminate the undesirable condition of the indeterminate state in the SR latch is to ensure that inputs S and R are never equal to 1 at the same time. This is done in the D latch •This latch has only two inputs: D (data) and En(enable). The D input goes directly to the S input, and its complement is applied to the R input. As long as the enable input is at 0, the cross-coupled SR latch has both inputs at the 1 level and the circuit cannot change state regardless of the value of D . •The state of a latch or flip-flop is switched by a change in the control input. •This momentary change is called a t r i g g e r, and the transition it causes is said to trigger the flip-flop. JK:- There are three operations that can be performed with a flip-flop: Set it to 1, reset it to 0, or complement its output. •With only a single input, the D flip-flop can set or reset the output, depending on the value of the D input immediately before the clock transition. The T (toggle) flip-flop is a complementing flip-flop and can be obtained from a JK flip-flop when inputs J and K are tied together