Say-Sist Multiplexer Deney3

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Say-Sist Multiplexer Deney3

Circuit Description

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The circuit switches two two-bit input data A and B for transmission to the output. When the data select (S) input is 0, the odd-numbered AND gates are masked keeping their output low regardless of the logic state of B. The even-numbered AND gates, on the other hand, follow the logic state of A. Therefore B is blocked while A is allowed to be transmitted. When S is 1, A is blocked while B is transmitted.

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Creator

B10

6 Circuits

Date Created

3 years, 6 months ago

Last Modified

3 years, 6 months ago

Tags

  • multiplexer
  • mux
  • two-bit multiplexer
  • two-input two-bit mux
  • 2-input 2-bit multiplexer
  • 2-input 2-bit mux
  • two-input multiplexer

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