SR Tleulinov N

The operation of the basic trigger can be changed by providing an additional control input that determines when the state of the circuit should be changed. We have an SR trigger with a clock pulse input. It consists of a basic trigger circuit and two additional NAND elements. The pulse input acts as a resolution signal for the other two inputs. The outputs of NAND elements 3 and 4 remain at logic level 1 until The CP input remains at 0. This is the resting state for the base trigger. When the pulse input goes to 1, information from the input S or R can flow to the output. The set state is reached at S = 1, R = 0 and CP = 1. This leads to the fact that the output of element 3 goes to 0, the output of element 4 remains at 1, and the output of the trigger in Q goes to 1. To go to the reset state, the inputs must be S = 0, R = 1 and CP = 1.