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SR -unable- ezzat (1)

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A simple SR latch using NAND gates. When Enable is1 and input SR is 00 - Memory State 01 - Reset 10 - Set 11 - Forbidden State

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ezzatahmed

76 Circuits

Date Created

1 year, 1 month ago

Last Modified

1 year, 1 month ago

Tags

  • digital electronics

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