JFET-N Gate Bias

A JFET-N Gate Bias Circuit. *A JFET is a normally open device. A negative voltage on gate reduces the drain current. *If Vgs is equal to Vp (or VTO), Id = 0. *This biasing is good for working in ohmic region. Not active (saturation) region. *Ohmic region: Vgs = 0 and Id(sat)<<Idss *Idss is the maximum drain current that a JFET is capabable of delivering. *In ohmic region, JFET behaves like a resistor with a resistance of about: Rds = Vp/Idss