Master-Slave J-K Flip-Flop
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Circuit Description
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The circuit is an interconnection of a J-K latch and an S-R flip-flop in master-slave configuration. This results to a negative-edge-triggered master-slave J-K flip-flop.
The 100 kΩ load resistors are not part of the Master-Slave J-K Flip-Flop, their purpose is to help initialize the output to known logic state. If simulation is started with clock (CLK) at low state, Q and not Q will be at undetermined state and this cannot be exited. If simulation is started with clock (CLK) at high state, Q and NOTQ will toggle regardless of the state of J and K. This can be exited by setting J and K at opposing states and setting CLK back to low. If the clock is set low with both J and K high, the output will continue to toggle but this can be exited by reclocking with opposing logic states at J and K. On the other hand, if clock is returned low with J=0=K, the undetermined state will persist and this cannot be exited.
After initialization the flip-flop will function as tabulated below:
NO CHANGE: J=0, K=0
RESET: J=0, K=1
SET: J=1, K=0
TOGGLE: J=1, K=1
Creator
GGoodwin
1116 Circuits
Date Created
5 years, 8 months ago
Last Modified
5 years, 8 months ago
Tags
Open Circuit
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