Constant Frequency Astable Multivibrator.veri

** 555-Constant Frequency Astable Multivibrator.veri ** * * Multisim Live SPICE netlist * * * --- Circuit Topology --- * Component: Cctl cCctl 6 0 1e-8 * Component: Ct cCt 1 0 1e-7 * Component: Dchg dDchg 2 3 1N4148_2_Dchg * Component: Ddchg dDdchg 4 5 1N4148_2_Ddchg * Component: Rchgmin rRchgmin 7 2 1000 VIRTUAL_RESISTANCE_Rchgmin * Component: Rdcadj xRdcadj 3 1 4 Potentiometer_Rdcadj PARAMS: res=10000 posPercent=50 * Component: Rdchgmin rRdchgmin 2 5 1000 VIRTUAL_RESISTANCE_Rdchgmin * Component: U1 xU1 0 1 OUT 7 6 1 2 7 IDEAL_TIMER_U1 * Component: Vcc vVcc 7 0 dc 5 ac 0 0 + distof1 0 0 + distof2 0 0 * --- Circuit Models --- * Dchg model .model 1N4148_2_Dchg d ( + IS=6.89131e-09 RS=0.636257 N=1.82683 EG=1.15805 + XTI=0.518861 BV=80 IBV=0.0001 CJO=9.99628e-13 + VJ=0.942987 M=0.727538 FC=0.5 TT=4.33674e-09 + KF=0 AF=1 ) * Ddchg model .model 1N4148_2_Ddchg d ( + IS=6.89131e-09 RS=0.636257 N=1.82683 EG=1.15805 + XTI=0.518861 BV=80 IBV=0.0001 CJO=9.99628e-13 + VJ=0.942987 M=0.727538 FC=0.5 TT=4.33674e-09 + KF=0 AF=1 ) * Rchgmin model .model VIRTUAL_RESISTANCE_Rchgmin r( ) * Rdchgmin model .model VIRTUAL_RESISTANCE_Rdchgmin r( ) * --- Subcircuits --- * Rdcadj subcircuit .subckt Potentiometer_Rdcadj T1 T2 T3 PARAMS: res=10k posPercent=50 .PARAM relPos = limit(posPercent * 0.01, 0.0000001, 0.9999999) r1 T1 T2 {{res}*relPos} r2 T2 T3 {{res} - {res}*relPos} .ends * U1 subcircuit .subckt IDEAL_TIMER_U1 0 2 3 4 5 6 7 8 rn1 8 5 5k rn2 5 51 5k rn3 51 0 5k Ecomp1 56x 0 value={if(v(5,6)>0,5,0)} Ecomp2 52x 0 value={if(v(2,51)>0,5,0)} **These prevent an unstable condition during DC OP EskipDC 52 0 value={if(TIME>0, v(52x), 0)} EskipDC2 56 0 value={if(TIME>0, v(56x), 0)} .model op limit (gain= 3000, + out_upper_limit=5, + out_lower_limit=-5, + limit_range=1 fraction=true) aadc1 [56 52] [r s] ADC1 .MODEL ADC1 adc_bridge (in_low= 3.5 in_high = 3.5 rise_delay= 1e-12 fall_delay= 1e-12) anand1 [r Q2] Q1 nand1 anand2 [s Q1] Q2 nand1 .model nand1 d_nand(rise_delay=1n) adac1 [q1 q2] [66 62] DAC1 rad3 66 0 1 rad4 62 0 1 aadc4 [4] [40] ADC1 ainv2 40 41 inv1 adlatch q1 2u 41 3d Qb Qc dlt .model dlt d_dlatch(rise_delay=1e-12) apu1 2u pullup1 .model pullup1 d_pullup(load=10e-12) apd1 3d pulldown1 .model pulldown1 d_pulldown(load=10e-12) ainv1 Qb 31 inv1 .model inv1 d_inverter(rise_delay=1e-12) adac72 [Qb] [72] DAC1 adac31 [31] [32] DAC1 r30 32 0 1g b1 3 0 v=(v(32)*v(8)/5) r3 3 0 1g .MODEL DAC1 dac_bridge (out_low= 0.0 out_high= 5.0 out_undef=0.5) rad5 72 0 1meg mdis 7 72 0 0 mdis .MODEL mdis nmos (VTO=1.29 PHI=0.4 LAMBDA=5 KP=4.3m LD=12.8u GAMMA =3)