Design 3_20

Improvement from Design 2 - Knowing CE with degeneration is better, I added R_E in CE stage - From the textbook, adding a C_E cap can improve bandwidth due to the Miller multiplier associated to this emitter capacitance. Therefore, C_E is added in parallel with R_E, connected to ground - Used UPenn Method to find Rc, R1, R2, and R3 based on chosen Ic of 1mA, beta of 100, V_A of 100V and desired Vo of 10V - UPenn method also has the |Av| = Rc / R_E ratio. So I let it be 20, and that's how I found R_E based on found Rc Problem: - When Rc/R_E = 20, Vo/Vsig = 2.6 - If Rc/R_E = 10, see Design 3_10