Lab 9 part 1

The circuit is a switched capacitor voltage doubler. When clock is high the switch Sw is in position 1, this connects the negative electrode of the flying/charge pump capacitor Ccp to ground and the positive electrode of Ccp to the positive terminal of power supply Vsp. This charges capacitor Ccp to Vsp. When clock is low the switch Sw is in position 2, this connects the negative electrode of capacitor Ccp to the positive terminal of power supply Vsp and the positive electrode of Ccp to the positive terminal of reservoir capacitor Cres. Thus, Ccp is placed in series with the power supply effectively doubling the voltage available to the output. Output/reservoir capacitor Cres is charged to this stacked voltage which it will provide to the load when clock returns high.