D Latch???

This is a modification of the circuit "NAND Set-Reset (S-R/R-S/SR/RS) Latch". To avoid the problem associated with simultaneous assertion of nSET and nRESET, these two input signals are now unified to a single input which is now designated as D. An additional inverter keeps the two input to the NAND latch always at opposing logic states. Thus, the condition which tend to both set and reset the latch at the same time is avoided. The alteration, however, creates a side-effect which makes the circuit practically useless. The Q output now simply follows the input and NOTQ is simply the complement of the input. Nevertheless, the modification in this circuit will be combined with that made in the circuit "Set-Reset (S-R/R-S/SR/RS) Latch With Enable" to create a true D latch which is in the circuit "(Gated) D Latch".