Browser not supported

✕
Go back

Tier limit reached

✕

"EET145_Lab_05_YYYYMMDD_Lastname-NAND" (2)

0
Favorite
1
copy
Copy
68
Views
Open Circuit
"EET145_Lab_05_YYYYMMDD_Lastname-NAND" (2)
Social Share
Embed circuit
Embed linked image

Circuit Description

Graph image for "EET145_Lab_05_YYYYMMDD_Lastname-NAND" (2)

Circuit Graph

This is a Set-Reset (S-R or RS) latch implemented using NAND gates.

There are currently no comments

Profile image for hunter422

EET145_Lab_05_20230309_Allison-NAND

hunter422

Creator

Profile image for hunter422

hunter422

8 Circuits

Date Created

1 year, 2 months ago

Last Modified

1 year, 2 months ago

Tags

  • nand latch
  • set-reset latch
  • nand rs latch
  • s-r latch
  • nand s-r latch
  • rs latch
  • latch

Circuit Copied From

"EET145_Lab_05_YYYYMMDD_Lastname-NAND"

Related Circuits

Preview of Master-Slave D Latch (Edge-Triggered D Flip-Flop) With Preset And Clear

Master-Slave D Latch (Edge-Triggered D Flip-Flop) With Preset And Clear

by GGoodwin

8484
0
copy
30
Preview of Master-Slave J-K Flip-Flop

Master-Slave J-K Flip-Flop

by GGoodwin

7498
1
copy
93
Preview of Master-Slave D Latch (Edge-Triggered D Flip-Flop)

Master-Slave D Latch (Edge-Triggered D Flip-Flop)

by GGoodwin

5228
0
copy
30

© 2024 National Instruments Corp. ALL RIGHTS RESERVED.

Hosted Services Terms Privacy Policy Export Notices Terms of Use

Circuit Graph

✕
Graph image for "EET145_Lab_05_YYYYMMDD_Lastname-NAND" (2)

Remove Comment

✕

Are you sure you want to remove your comment? This action cannot be undone.

Cancel Remove Comment

✕
Cancel Send

Enter Email

✕