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JK flip-flops

JK Flip-Flop POSSR

This component is a JK flip-flop with  set, reset and complementary outputs.  The J and K inputs must be stable prior to the LOW-to-HIGH clock transition for predictable operation. The set and reset are asynchronous active high inputs. When high, they override the clock and data inputs forcing the outputs to the steady state levels.

JK flip flop conpane.PNG

Function table

Inputs Outputs
SET RESET CLK J K Q ~Q
L
H
X X X
L
H
H
L
X X X H
L
H

X X X NS
NS
L
L
L
L
NO CHANGE
L
L
L
H
L
H
L
L
H
L
H
L
L
L
H
H
TOGGLE

   

   

     H = HIGH Level

     L = LOW Level

     X = Don't Care

     ↑  = LOW-to-HIGH Clock  transition

     NS = Not Stable state of the   outputs  when both SET and RESET   inputs are HIGH

     SET, RESET = Asynchronous Inputs

JK Flip-Flop NEGSR

This component is a JK flip-flop with  set, reset and complementary outputs.  The J and K inputs must be stable prior to the LOW-to-HIGH clock transition for predictable operation. The set and reset are asynchronous active low inputs. When low, hey override the clock and data inputs forcing the outputs to the steady state levels.

JK FF NEGSR

Function table

Inputs Outputs
SET RESET CLK J K Q ~Q
H
L
X X X
L
H
L
H
X X X H
L
L
L
X X X NS
NS
H
H
L
L
NO CHANGE
H
H
L
H
L
H
H
H
H
L
H
L
H
H
H
H
TOGGLE

   

   

     H = HIGH Level

      L = LOW Level

      X = Don't Care

      ↑  = LOW-to-HIGH Clock  transition

      NS = Not Stable state of the   outputs  when both SET and RESET   inputs are LOW

     SET, RESET = Asynchronous Inputs